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参数资料
| 型号： | DC1367A |
| 厂商： | Linear Technology |
| 文件页数： | 14/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL LTM4615 |
| 软件下载： | LTM4615 |
| 设计资源： | DC1367A Design Files DC1367A Schematic |
| 标准包装： | 1 |
| 系列： | LTM®, uModule® |
| 主要目的： | DC/DC，LDO 步降 |
| 输出及类型： | 3，非隔离 |
| 输出电压： | 1.8V，1.2V，1V |
| 电流 - 输出： | 4A，2.5A，1.5A |
| 输入电压： | 2.5 ~ 5.5 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 1.25MHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | LTM4615 |
| 相关产品： | LTM4615EV#PBF-ND - IC SWIT REG BUCK 4A ADJ 144LGA LTM4615IV#PBF-ND - IC SWIT REG BUCK 4A ADJ 144LGA |
LTM4615
APPLICATIONS INFORMATION
VLDO SECTION
Adjustable Output Voltage
The output voltage is set by the ratio of two resistors. A
4.99k resistor is built onboard the module from LDO_OUT
to FB3. An additional resistor (R FBLDO )is required from FB3
to GND3 to set the output voltage over a range of 0.4V to
2.6V. Minimum output current of 1mA is required for full
output voltage range.
pacitance can be used, but a ceramic capacitor must be
used in parallel at the output.
Extra consideration should be given to the use of ceramic
capacitors related to dielectrics, temperature and DC bias
effects on the capacitor. The VLDO requires a minimum
10μF value. The X7R and X5R dielectrics are more stable
with DC bias and temperature, thus more preferred.
Short-Circuit/Thermal Protection
R FBLDO =
Theequation:
V LDO _ OUT = 0.4V ?
or equivalently,
4.99k
V LDO _ OUT
0.4V
4.99k + R FBLDO
R FBLDO
? 1
The VLDO has built-in short-circuit current limiting of
~3A as well as overtemperature protection. During short-
circuit conditions the device is in control to 3A, and as
the internal temperature rises to approximately 150°C,
then the internal boost and LDO are shut down until the
internal temperature drops back to 140°C. The device will
cycle in and out of this mode with no latchup or damage.
Long term over stress in this condition can degrade the
device over time.
LDO_IN VOLTAGE (V)
PowerGoodOperation
The VLDO includes an open-drain power good (PGOOD3)
pin with hysteresis. If the VLDO is in shutdown or under
UVLO conditions (BOOST3 < 4.2V), then PGOOD3 is low
impedance to ground. PGOOD3 becomes high imped-
ance when the VLDO output voltage rises to 93% of its
regulated voltage. PGOOD3 stays high impedance until
the output voltage falls to 91% of its regulated voltage. A
pull-up resistor can be inserted between the PGOOD3 pin
and a positive logic supply such as the VLDO output or
V IN . LDO_IN should be at least 1.14V or greater for power
good to operate properly.
Output Capacitance and Transient Response
The VLDO is designed to be stable with a wide range of
ceramic output capacitors. The ESR of the output capaci-
tors affects stability, especially smaller value capacitors. An
output capacitor of 10μF or greater with an ESR of 0.05Ω
or less is recommended to ensure stability. Larger value
capacitors can be used to reduce the transient deviations
under load changes. Bypass capacitors that are used at
the load device can also increase the effective output
capacitance. High ESR tantalum or electrolytic bulk ca-
Reverse Current Protection
The VLDO features reverse current protection to limit
current draw from any supplementary power source at
the output. Figure 4 shows the reverse input current limit
versus input voltage for a nominal V LDO_OUT setpoint of
1.5V. Note: Positive input current represents current flow-
ing into the LDO_IN pin. With LDO_OUT held at or below
the output regulation voltage and LDO_IN varied, input
current flow will follow the Figure 4 curve. Input reverse
current ramps up to 16μA as LDO_IN approaches LDO_OUT.
30
IN CURRENT
20 LIMIT ABOVE 1.45V
10
0
–10
–20
–30
0 0.3 0.6 0.9 1.2 1.5 1.8
4615 F04
Figure 4. Reverse Current Limit for VLDO
14
For more information www.linear.com/LTM4615
4615fb
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