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| 型号： | DC745A |
| 厂商： | Linear Technology |
| 文件页数： | 17/28页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2433-1 |
| 软件下载： | QuikEval System |
| 设计资源： | DC745A Design File DC745A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 2 |
| 位数： | 16 |
| 采样率（每秒）： | 6.8 |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 工作温度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2433-1 |
| 已供物品： | 板 |
| 相关产品： | LTC2433-1IMS#PBF-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP LTC2433-1CMS#TRPBF-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP LTC2433-1IMS#TRPBF-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP LTC2433-1CMS#PBF-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP LTC2433-1IMS#TR-ND - IC CONV A/D 16BIT DIFF 10-MSOP LTC2433-1CMS#TR-ND - IC CONV A/D 16BIT DIFF 10-MSOP LTC2433-1IMS-ND - IC CONV A/D 16BIT DIFF 10-MSOP LTC2433-1CMS-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP |
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LTC2433-1
24
24331fa
translates into about 7.15 10–6 fEOSCLSB additional INL
error. Figure 23 shows the typical INL error due to the
source resistance driving the REF+ or REF– pins when
large CREF values are used. The effect of the source
resistance on the two reference pins is additive with
respect to this INL error. In general, matching of source
impedance for the REF+ and REF– pins does not help the
gain or the INL error. The user is thus advised to minimize
the combined source impedance driving the REF+ and
REF– pins rather than to try to match it.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typical better than
0.5%. Such a specification can also be easily achieved by
an external clock. When relatively stable resistors
(50ppm/
°C) are used for the external source impedance
seen by REF+ and REF–, the expected drift of the dynamic
current gain error will be insignificant (about 1% of its
value over the entire temperature and voltage range). Even
for the most stringent applications a one-time calibration
operation may be sufficient.
In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(
±10nA max), results in a small gain error. A 100 source
resistance will create a 0.05
V typical and 0.5V maxi-
mum full-scale error.
Output Data Rate
When using its internal oscillator, the LTC2433-1 can
produce up to 6.8 readings per second. The actual output
data rate will depend upon the length of the sleep and data
output phases which are controlled by the user and which
can be made insignificantly short. When operated with an
external conversion clock (FO connected to an external
oscillator), the LTC2433-1 output data rate can be in-
creased as desired. The duration of the conversion phase
is 20510/fEOSC. If fEOSC = 139,800Hz, the converter be-
haves as if the internal oscillator is used with simultaneous
50Hz/60Hz. There is no significant difference in the
LTC2433-1 performance between these two operation
modes.
An increase in fEOSC over the nominal 139,800Hz will
translate into a proportional increase in the maximum
output data rate. This substantial advantage is neverthe-
less accompanied by three potential effects, which must
be carefully considered.
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent perfor-
mance degradation can be substantially reduced by rely-
ing upon the LTC2433-1’s exceptional common mode
rejection and by carefully eliminating common mode to
differential mode conversion sources in the input circuit.
The user should avoid single-ended input filters and
should maintain a very high degree of matching and
symmetry in the circuits driving the IN+ and IN– pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
Figure 23. INL vs Differential Input Voltage (VIN = IN
+ – IN–)
and Reference Source Resistance (RSOURCE at REF+ and REF–
for Large CREF Values (CREF ≥ 1F)
VINDIF/VREFDIF
–0.5 –0.4–0.3–0.2–0.1 0
0.1 0.2 0.3 0.4 0.5
INL
(LSB)
1
0
–1
VCC = 5V
REF+ = 5V
REF– = GND
VINCM = 0.5 (IN
+ + IN–) = 2.5V
FO = GND
CREF = 10F
TA = 25°C
RSOURCE = 1000
24331 F23
APPLICATIO S I FOR ATIO
WU
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