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| 型号： | DC745A |
| 厂商： | Linear Technology |
| 文件页数： | 7/28页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2433-1 |
| 软件下载： | QuikEval System |
| 设计资源： | DC745A Design File DC745A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 2 |
| 位数： | 16 |
| 采样率（每秒）： | 6.8 |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 工作温度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2433-1 |
| 已供物品： | 板 |
| 相关产品： | LTC2433-1IMS#PBF-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP LTC2433-1CMS#TRPBF-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP LTC2433-1IMS#TRPBF-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP LTC2433-1CMS#PBF-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP LTC2433-1IMS#TR-ND - IC CONV A/D 16BIT DIFF 10-MSOP LTC2433-1CMS#TR-ND - IC CONV A/D 16BIT DIFF 10-MSOP LTC2433-1IMS-ND - IC CONV A/D 16BIT DIFF 10-MSOP LTC2433-1CMS-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP |
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LTC2433-1
15
24331fa
Figure 8. External Serial Clock, CS = 0 Operation (2-Wire)
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 8. CS
may be permanently tied to ground, simplifying the user
interface or isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
typically 1ms after VCC exceeds 2V. The level applied to
SCK at this time determines if SCK is internal or external.
SCK must be driven LOW prior to the end of POR in order
to enter the external serial clock timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is ready.
EOC = 1 while the conversion is in progress and EOC = 0
once the conversion ends. On the falling edge of EOC, the
conversion result is loaded into an internal static shift reg-
ister. Data is shifted out the SDO pin on each falling edge
of SCK enabling external circuitry to latch data on the ris-
ing edge of SCK. EOC can be latched on the first rising edge
of SCK. On the 19th falling edge of SCK, SDO goes HIGH
(EOC = 1) indicating a new conversion has begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 9.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state during the EOC test. In
order to allow the device to return to the low power sleep
state, CS must be pulled HIGH before the first rising edge
of SCK. In the internal SCK timing mode, SCK goes HIGH
EOC
BIT 18
SDO
SCK
(EXTERNAL)
CS
MSB
SIG
“O”
BIT 0
LSB
BIT 2
BIT 1
BIT 14
BIT 13
BIT 15
BIT 16
BIT 17
DATA OUTPUT
CONVERSION
24331 F08
CONVERSION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
VCC
FO
REF+
REF–
SCK
IN+
IN–
SDO
GND
CS
110
2
3
9
4
5
8
6
7
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1
F
2.7V TO 5.5V
LTC2433-1
3-WIRE
SPI INTERFACE
APPLICATIO S I FOR ATIO
WU
UU
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