参数资料
型号: DK-DEV-2AGX260N
厂商: Altera
文件页数: 19/48页
文件大小: 0K
描述: KIT DEV FPGA 2AGX260 W/6.375G TX
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 1
系列: Arria II GX
类型: FPGA
适用于相关产品: EP2AGX260
所含物品: 板,线缆,CD,DVD,电源
产品目录页面: 605 (CN2011-ZH PDF)
其它名称: 544-2696
5. Board Update Portal
Introduction
The Arria II GX FPGA Development Kit, 6G Edition ships with the Board Update
Portal design example stored in the factory portion of the flash memory on the board.
The design consists of a Nios II embedded processor, an Ethernet MAC, and an
HTML web server.
When you power up the board with the USR LOAD switch (SW4.4) in the off position,
the Arria II GX FPGA configures with the Board Update Portal design example. The
design can obtain an IP address from any DHCP server and serve a web page from the
flash on your board to any host computer on the same network. The web page allows
you to upload new FPGA designs to the user hardware 1 portion of flash memory,
and provides links to useful information on the Altera website, including links to
kit-specific and design resources.
1
After successfully updating the user hardware 1 flash memory, you can load the user
design from flash memory into the FPGA. To do so, set the USR LOAD switch (SW4.4)
to the on position and power cycle the board.
The source code for the Board Update Portal design resides in the <install
dir> \kits\arriaIIGX_2agx260_fpga\examples directory. If the Board Update Portal is
corrupted or deleted from the flash memory, refer to “Restoring the Flash Device to
the Factory Settings” on page A–4 to restore the board with its original factory
contents.
Connecting to the Board Update Portal Web Page
This section provides instructions to connect to the Board Update Portal web page.
1
Before you proceed, ensure that you have the following:
A PC with a connection to a working Ethernet port on a DHCP enabled network.
A separate working Ethernet port connected to the same network for the board.
The Ethernet and power cables that are included in the kit.
To connect to the Board Update Portal web page, perform the following steps:
1. With the board powered down, set the USR LOAD switch (SW4.4) to the off
position.
2. Attach the Ethernet cable from the board to your LAN.
3. Power up the board. The board connects to the LAN’s gateway router, and obtains
an IP address. The LCD on the board displays the IP address.
4. Launch a web browser on a PC that is connected to the same network, and enter
the IP address from the LCD into the browser address bar. The Board Update
Portal web page appears in the browser.
July 2010 Altera Corporation
Arria II GX FPGA Development Kit, 6G Edition User Guide
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