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参数资料
| 型号： | DK-DEV-2AGX260N |
| 厂商： | Altera |
| 文件页数： | 45/48页 |
| 文件大小： | 0K |
| 描述： | KIT DEV FPGA 2AGX260 W/6.375G TX |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 1 |
| 系列： | Arria II GX |
| 类型： | FPGA |
| 适用于相关产品： | EP2AGX260 |
| 所含物品： | 板，线缆，CD，DVD，电源 |
| 产品目录页面： | 605 (CN2011-ZH PDF) |
| 其它名称： | 544-2696 |
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Chapter :
A–5
Restoring the MAX II CPLD to the Factory Settings
12. Cycle the POWER switch (SW1) off then on to load and run the restored factory
design.
13. The restore script cannot restore the board’s MAC address automatically. In the
Nios II command shell, type the following Nios II EDS command:
nios2-terminal r
and follow the instructions in the terminal window to generate a unique MAC
address.
f To ensure that you have the most up-to-date factory restore files and information
about this product, refer to the Arria II GX FPGA Development Kit, 6G Edition page
of the Altera website.
Restoring the MAX II CPLD to the Factory Settings
This section describes how to restore the original factory contents to the MAX II CPLD
on the FPGA development board, 6G edition. Make sure you have the Nios II EDS
installed, and perform the following instructions:
1
Uninstalling the shunt jumper from jumper J9 pins 1-2 includes the MAX II
device in the JTAG chain.
2. Launch the Quartus II Programmer.
3. Click Auto Detect .
4. Click Add File and select <install
dir> \kits\arriaIIGX_2agx260_fpga\factory_recovery\max2.pof .
5. Turn on the Program/Configure option for the added file.
6. Click Start to download the selected configuration file to the MAX II CPLD.
Configuration is complete when the progress bar reaches 100%.
f To ensure that you have the most up-to-date factory restore files and information
about this product, refer to the Arria II GX FPGA Development Kit, 6G Edition page
of the Altera website.
July 2010 Altera Corporation
Arria II GX FPGA Development Kit, 6G Edition User Guide
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