参数资料
型号: DK-DEV-4SGX530N
厂商: Altera
文件页数: 29/58页
文件大小: 0K
描述: KIT DEVELOPMENT STRATIX IV
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 1
系列: Stratix® IV GX
类型: FPGA
适用于相关产品: Stratix? IV GX
所含物品: 板,线缆,文档,电源
其它名称: 544-2714
Chapter 6: Board Test System
Using the Board Test System
6–5
MAX II ver —Indicates the version of MAX II code currently running on the board.
The MAX II code resides in the <install
dir> \kits\stratixIVGX_4sgx230_fpga\examples directory. Newer revisions of
this code might be available on the Stratix IV GX FPGA Development Kit page of
the Altera website.
MAC —Indicates the MAC address of the board.
MAX II Registers
The MAX II registers control allows you to view and change the current MAX II
register values as described in Table 6–1 . Changes to the register values with the GUI
take effect immediately. For example, writing a 0 to SRST resets the board.
Table 6–1. MAX II Registers
Register Name
System Reset
(SRST)
Page Select Register
(PSR)
Page Select Override
(PSO)
Read/Write
Capability
Write only
Read / Write
Read / Write
Description
Set to 0 to initiate an FPGA reconfiguration.
Determines which of the up to eight (0-7) pages of flash
memory to use for FPGA reconfiguration. The flash memory
ships with pages 0 and 1 preconfigured.
When set to 0, the value in PSR determines the page of
flash memory to use for FPGA reconfiguration. When set to
1, the value in PSS determines the page of flash memory to
use for FPGA reconfiguration.
Page Select Switch
(PSS)
Read only
Holds the current value of the rotary switch (SW2).
PSO —Sets the MAX II PSO register. The following options are available:
Use PSR —Allows the PSR to determine the page of flash memory to use for
FPGA reconfiguration.
Use PSS —Allows the PSS to determine the page of flash memory to use for
FPGA reconfiguration.
PSR —Sets the MAX II PSR register. The numerical values in the list corresponds to
the page of flash memory to load during FPGA reconfiguration. Refer to Table 6–1
for more information.
PSS —Displays the MAX II PSS register value. Refer to Table 6–1 for the list of
available options.
SRST —Resets the system and reloads the FPGA with a design from flash memory
based on the other MAX II register values. Refer to Table 6–1 for more information.
1
Because the Config tab requires that a specific design is running in the FPGA, writing
a 0 to SRST or changing the PSO value can cause the Board Test System to stop
running.
JTAG Chain
The JTAG chain control shows all the devices currently in the JTAG chain. The
Stratix IV GX device is always the first device in the chain.
March 2014
Altera Corporation
Stratix IV GX FPGA Development Kit User Guide
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