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| 型号： | DK-DEV-4SGX530N |
| 厂商： | Altera |
| 文件页数： | 40/58页 |
| 文件大小： | 0K |
| 描述： | KIT DEVELOPMENT STRATIX IV |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 1 |
| 系列： | Stratix® IV GX |
| 类型： | FPGA |
| 适用于相关产品： | Stratix? IV GX |
| 所含物品： | 板，线缆，文档，电源 |
| 其它名称： | 544-2714 |
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6–16
Chapter 6: Board Test System
Using the Board Test System
Start
The Start control initiates HSMC transaction performance analysis.
Stop
The Stop control terminates transaction performance analysis.
Performance Indicators
These controls display current transaction performance analysis information collected
since you last clicked Start :
■
■
TX and RX performance bars—Show the percentage of maximum theoretical data
rate that the requested transactions are able to achieve.
Tx (MBps) and Rx (MBps) —Show the number of bytes of data analyzed per
second. The transceiver buses are 4 bits (serial channels) wide and clocked using
the 100 MHz oscillator with a PLL multiplier of 20, so the data rate is 2 Gbps,
totaling 8 MBps per transceiver port. The LVDS SERDES bus is 17 bits wide. The
HSMC x17 SERDES buses on both HSMC A and HSMC B are 17 bits wide and
clocked using the 125 MHz oscillator with a PLL multiplier of 13, equating to a
1.625 Gbps per pin, or a 27.625 Gbps bandwidth for each x17 SERDES port. The x3
single-ended data bus is 3 bits wide and clocked using a 50 MHz clock single-data-
rate for 50 Mbps per pin, or a 150 Mbps bandwidth for each x3 single-ended data
port.
1
1
Performance figures are based on a 100-MHz input clock from
programmable oscillator X6. Using the “The Clock Control” on page 6–22 to
adjust the frequency changes the circuit speed in real time and the HSMC
tab performance indicators, which are capped at 100% for increased
frequencies. Physical layer speeds equal the oscillator X6 frequency times
the input PLL multiplier ratio. The default is 2 GHz (100 MHz × 20) or
2 Gbps per pin or 8 Gbps total. Changing the oscillator X6 frequency to
400 MHz changes the circuit speed to 8 GHz or 32 Gbps total. Typically you
need to reset the HSMC design after changing the clock frequency.
The HSMC x17 SERDES and x3 single-ended ports use fixed frequency
oscillators and are not affected by the Clock Control application.
Stratix IV GX FPGA Development Kit User Guide
March 2014 Altera Corporation
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| DK-DEV-5AGXB3N/ES | ARRIA V DEVELOPMENT KIT |
| DK-DEV-5M570ZN | KIT DEV MAX V 5M570Z |
| DK-DEV-5SGXEA7N | KIT DEV STRATIX V FPGA 5SGXEA7 |
| DK-DSP-2S180N | DSP PRO KIT W/SII EP2S180N |
| DK-DSP-3C120N | KIT DEV DSP CYCLONE III EDITION |
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| DK-DEV-5AGTD7N | 功能描述:可编程逻辑 IC 开发工具 FPGA Development Kit For 5AGTD7K3F40I3N RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
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| DK-DEV-5ASTD5N | 功能描述:KIT DEV ARRIA V FPGA 制造商:altera 系列:Arria V ST 零件状态:在售 类型:FPGA 配套使用产品/相关产品:Arria? V ST 内容:板 标准包装:1 |
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