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参数资料
| 型号： | DS1023S-50/T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 12/16页 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 256TAP 16-SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1,000 |
| 标片/步级数： | 256 |
| 功能： | 单发射，可编程 |
| 延迟到第一抽头： | 16.5ns |
| 接头增量： | 0.5ns |
| 可用的总延迟： | 127.5ns |
| 独立延迟数： | 1 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 带卷 (TR) |
DS1023
5 of 16
MS = 1 Figure 4
Output Function
Name
Pin Number
Pulse Width Modulated Output
PWM
9
Delayed and Inverted Output
OUT
15
PWM is an output triggered by the rising edge of the input waveform. After a time interval approximately
equal to the Step Zero delay of the device the PWM output will go high. The output will return to a low
level after a time interval determined by the programmed values (Table 1). Hence output pulse widths can
be obtained from (nearly) zero to the full delay range of the device. In practice the minimum output pulse
width is limited by the response time of the device to approximately 5ns. Programmed values less than
this will result in degradation of the output high level voltage until ultimately no discernible output pulse
is produced. The frequency/repetition rate of the output is determined by the input frequency. The input
pulse width can be shorter than the output pulse width, and is limited only by the minimum input pulse
width specification. The PWM function is not “re-triggerable”, subsequent input trigger pulses should
not be present until the output has returned to a low level.
OUT
is an inverted copy of the input waveform that is delayed by an amount set by the programmed
values (Table 1). A programmed value of zero will still result in a non-zero delay as indicated in the Step
Zero delay specification. The OUT pin may also be externally connected to the input pin to produce a
free-running oscillator. The frequency of oscillation is determined by the programmed delay value of the
device (see Table 2).
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