参数资料
型号: DS1225Y
厂商: DALLAS SEMICONDUCTOR
元件分类: DRAM
英文描述: 64K Nonvolatile SRAM(64K 非易失性静态RAM)
中文描述: 8K X 8 NON-VOLATILE SRAM MODULE, 200 ns, PDIP28
文件页数: 6/8页
文件大小: 84K
代理商: DS1225Y
DS1225Y
021998 6/8
POWER–DOWN/POWER–UP CONDITION
3.2V
DATA RETENTION TIME
CE
V
CC
t
F
t
PD
t
R
t
REC
t
DR
LEAKAGE CURRENT
I
SUPPLIED FROM
LITHIUM CELL
V
TP
SEE NOTE 11
POWER–DOWN/POWER–UP TIMING
PARAMETER
SYM
MIN
MAX
UNITS
NOTES
CE at V
IH
before Power–Down
t
PD
0
μ
s
11
V
CC
Slew from V
TP
to 0V
t
F
100
μ
s
V
CC
Slew from 0V to V
TP
t
R
0
μ
s
CE at V
IH
after Power–Up
t
REC
2
ms
(t
A
= 25
°
C)
NOTES
PARAMETER
SYM
MIN
MAX
UNITS
Expected Data Retention Time
t
DR
10
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
NOTES:
1. WE is high for a read cycle.
2. OE = V
IH
or V
IL
. If OE = V
IH
during a write cycle, the output buffers remain in a high impedance state.
3. t
WP
is specified as the logical AND of CE and WE. t
WP
is measured from the latter of CE or WE going low to the
earlier of CE or WE going high.
4. t
DS
is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output
buffers remain in a high impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain
in a high impedance state during this period.
相关PDF资料
PDF描述
DS1230AB(中文) 256K NV SRAM(256K非易失性SRAM)
DS1230W 3.3V 256K Nonvolatile SRAM(3.3V 256K 非易失性静态RAM)
DS1230Y 256K Nonvolatile SRAM(256K 非易失性静态RAM)
DS1230AB 256K NV SRAM(256K非易失性SRAM)
DS1231 Power Monitor Chip(电源监控芯片)
相关代理商/技术参数
参数描述
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