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| 型号： | DS1230Y-200+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 2/10页 |
| 文件大小： | 0K |
| 描述： | IC NVSRAM 256KBIT 200NS 28DIP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 12 |
| 格式 - 存储器： | RAM |
| 存储器类型： | NVSRAM（非易失 SRAM） |
| 存储容量： | 256K (32K x 8) |
| 速度： | 200ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 28-DIP 模块（0.600"，15.24mm） |
| 供应商设备封装： | 28-EDIP |
| 包装： | 管件 |
| 产品目录页面： | 1432 (CN2011-ZH PDF) |
DS1230Y/AB
DESCRIPTION
The DS1230 256k Nonvolatile SRAMs are 262,144-bit, fully static, nonvolatile SRAMs organized as
32,768 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry
which constantly monitors V CC for an out-of-tolerance condition. When such a condition occurs, the
lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. DIP-package DS1230 devices can be used in place of existing 32k x 8 static
RAMs directly conforming to the popular bytewide 28-pin DIP standard. The DIP devices also match the
pinout of 28256 EEPROMs, allowing direct substitution while enhancing performance. DS1230 devices
in the Low Profile Module package are specifically designed for surface-mount applications. There is no
limit on the number of write cycles that can be executed and no additional support circuitry is required for
microprocessor interfacing.
READ MODE
The DS1230 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 15 address inputs
(A 0 - A 14 ) defines which of the 32,768 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within t ACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later-occurring signal ( CE or OE ) and the limiting
parameter is either t CO for CE or t OE for OE rather than address access.
WRITE MODE
The DS1230 devices execute a write cycle whenever the WE and CE signals are active (low) after
address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must
be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(t WR ) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then
WE will disable the outputs in t ODW from its falling edge.
DATA RETENTION MODE
The DS1230AB provides full functional capability for V CC greater than 4.75 volts and write protects by
4.5 volts. The DS1230Y provides full functional capability for V CC greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of V CC without any additional support circuitry.
The nonvolatile static RAMs constantly monitor V CC . Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high-
impedance. As V CC falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when V CC rises above approximately 3.0 volts
the power switching circuit connects external V CC to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after V CC exceeds 4.75 volts for the DS1230AB and 4.5 volts for the
DS1230Y.
FRESHNESS SEAL
Each DS1230 device is shipped from Maxim with its lithium energy source disconnected, guaranteeing
full energy capacity. When V CC is first applied at a level greater than 4.25 volts, the lithium energy source
is enabled for battery back-up operation.
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| ACM40DTMI-S189 | CONN EDGECARD 80POS R/A .156 SLD |
| DS1230YP-70+ | IC NVSRAM 256KBIT 70NS 34PCM |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1230Y-200+ | 功能描述:NVRAM 256k Nonvolatile SRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1230Y-200IND | 功能描述:NVRAM 256k Nonvolatile SRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1230Y-200-IND | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:256k Nonvolatile SRAM |
| DS1230Y-200IND+ | 功能描述:NVRAM 256k Nonvolatile SRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1230Y-55 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:NVRAM (Battery Based) |
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