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参数资料
| 型号： | DS1236 |
| 厂商： | DALLAS SEMICONDUCTOR |
| 元件分类： | 电源管理 |
| 英文描述： | MicroManager Chip(微管理器芯片) |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP16 |
| 封装： | 0.300 INCH, DIP-16 |
| 文件页数： | 10/19页 |
| 文件大小： | 210K |
| 代理商： | DS1236 |
DS1236
022698 10/19
power-down in CMOS mode. As V
CC
falls, the IN pin
voltage drops below V
TP
. As a result, the processor is
notified of an impending power failure via an active NMI,
which allows it to enter a sleep mode. As the power falls
further, V
CC
crosses V
CCTP
, the power monitor trip
point. Since the DS1236 is in CMOS mode, no reset is
generated. The RST voltage will follow V
CC
down, but
will fall no further than V
BAT
. At this time, CEO is brought
high to write protect the RAM. When the V
CC
reaches
V
BAT
, a power fail is issued via the PF and PF pins.
Figure 11 illustrates operation of the power-down se-
quence in NMOS mode. Once again, as power falls, an
NMI is issued. This gives the processor time to save crit-
ical data in nonvolatile SRAM. When V
CC
reaches
V
CCTP
, an active RST and RST are given. The RST volt-
age will follow V
CC
as it falls. CEO, PF, and PF will oper-
ate in a similar manner to CMOS mode. Notice that the
NMI will tri-state to prevent a loss of battery power.
Figure 12 shows the power-up sequence for the NMOS
mode. As V
CC
slews above V
BAT
, the PF and PF pins
are deactivated. An active reset occurs as well as an
NMI. Although the NMI may be short due to slew rates,
reset will be maintained for the standard t
RST
time-out
period. At a later time, if the IN pin falls below V
TP
, a new
NMI will occur. If the processor does not issue a ST, a
watchdog reset will also occur. The second NMI and
RST are provided to illustrate these possibilities.
Figure 13 illustrates the power-up timing for CMOS
mode. The principal difference is that the DS1236 is-
sues a reset immediately in the NMOS mode. In CMOS
mode, a reset is issued when IN rises above V
TP
. De-
pending on the processor type, the NMI may terminate
the Stop mode in the processor.
WAKE CONTROL/SLEEP CONTROL
The Wake/Sleep Control input (WC/SC) allows the pro-
cessor to disable all comparators on the DS1236 before
entering the Stop mode. This feature allows the
DS1236, processor, and static RAM to maintain nonvo-
latility in the lowest power mode possible. The proces-
sor may invoke the sleep mode in battery-operated
applications to conserve battery capacity when an ab-
sence of activity is detected. The operation of this signal
is shown in Figure 14. The DS1236 may subsequently
be restarted by a high-to-low transition on the PBRST
input through human interface via a keyboard, touch-
pad, etc. The processor will then be restarted as the
watchdog times out and drives RST and RST active.
The DS1236 can also be started up by forcing the
WC/SC pin high from an external source. Also, if the
DS1236 is placed in a sleep mode by the processor and
system power is lost, the DS1236 will wake up the next
time V
CC
rises above V
BAT
. These possibilities are illus-
trated in Figure 15.
When the sleep mode is invoked during normal pow-
er-valid conditions, all operation on the DS1236 is dis-
abled, thus leaving the NMI, RST, and RST outputs dis-
abled as well as the ST and IN inputs. However, a loss of
power during a sleep mode will result in an active RST
and RST when the RC pin is grounded (NMOS mode). If
the RC pin is tied high, the RST and RST pins will remain
inactive during power-down in a sleep mode. Removal
of the sleep mode by the PBRST input is not affected by
the IN pin threshold at V
TP
when the RC pin is tied high
(CMOS mode). Subsequent power-up of the V
CC
sup-
ply with the RC pin tied high will activate the RST and
RST outputs as the main supply rises above V
BAT
. A
high-to-low transition on the WC/SC pin must follow a
high-to-low transition on the ST pin by t
WC
to invoke a
Sleep mode for the DS1236.
相关PDF资料 |
PDF描述 |
|---|---|
| DS1238A | MicroManager(微管理器芯片) |
| DS1238 | MicroManager(微管理器芯片) |
| DS1239 | MicroManager Chip(微管理器芯片) |
| DS1250AB | 4096K Nonvolatile SRAM(4096K 非易失性静态RAM) |
| DS1250Y | 4096K Nonvolatile SRAM(4096K 非易失性静态RAM) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1236+5 | 功能描述:监控电路 RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| DS1236-10 | 功能描述:监控电路 RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| DS1236-10+ | 功能描述:监控电路 RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| DS1236-10N | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Power Supply Supervisor |
| DS1236-5 | 功能描述:监控电路 RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
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