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参数资料
| 型号： | DS1236 |
| 厂商： | DALLAS SEMICONDUCTOR |
| 元件分类： | 电源管理 |
| 英文描述： | MicroManager Chip(微管理器芯片) |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP16 |
| 封装： | 0.300 INCH, DIP-16 |
| 文件页数： | 5/19页 |
| 文件大小： | 210K |
| 代理商： | DS1236 |
DS1236
022698 5/19
If the IN pin is connected to V
CCO
, the NMI output will
pulse low as V
CC
decays to V
CCTP
in the NMOS mode
(RC=0). In the CMOS mode (RC=V
CCO
) the pow-
er-down of V
CC
out-of-tolerance at V
CCTP
will not pro-
duce a pulse on the NMI pin. Given that any NMI pulse
has been completed by the time V
CC
decays to V
CCTP
,
the NMI pin will remain high. The NMI voltage will follow
V
CC
down until V
CC
decays to V
BAT
. Once V
CC
decays
to V
BAT
, the NMI pin will either remain at V
OHL
or enter
tri-state mode as determined by the RC pin (see “Reset
Control” section).
MEMORY BACKUP
The DS1236 provides all of the necessary functions re-
quired to battery back a static RAM. First, a switch is
provided to direct SRAM power from the incoming 5 volt
supply (V
CC
) or from an external battery (V
BAT
), which-
ever is greater. This switched supply (V
CCO
) can also be
used to battery back a CMOS microprocessor. For more
information about nonvolatile processor applications,
review the “Reset Control” and “Wake Control” sections.
Second, the same power fail detection described in the
power monitor section is used to hold the chip enable
output (CEO) to within 0.3 volts of V
CC
or to within 0.7
volts of V
BAT
. This write protection mechanism occurs
as V
CC
falls below V
CCTP
as specified. If CEI is low at
the time power fail detection occurs, CEO is held in its
present state until CEI is returned high, or the period t
CE
expires. This delay of write protection until the current
memory cycle is completed prevents the corruption of
data. If CEO is in an inactive state at the time of V
CC
fail
detection, CEO will be unconditionally disabled within
t
CF
. During nominal supply conditions CEO will follow
CEI with a maximum propagation delay of 20 ns.
Figure 7 shows a typical nonvolatile SRAM application.
FRESHNESS SEAL
In order to conserve battery capacity during storage
and/or shipment of an end system, the DS1236 pro-
vides a freshness seal to electrically disconnect the bat-
tery. Figure 8 depicts the three pulses below ground on
the IN pin required to invoke the freshness seal. The
freshness seal will be disconnected and normal opera-
tion will begin when V
CC
is cycled and reapplied to a lev-
el above V
BAT
.
To prevent negative pulses associated with noise from
setting the freshness mode in system applications, a se-
ries diode and resistor can be used to shunt noise to
ground. During manufacturing, the freshness seal can
still be set by holding TP2 at -3 volts while applying the 0
to -3 volt clock to TP1.
POWER SWITCHING
When larger operating currents are required in a bat-
tery-backed system, the 5-volt supply and battery sup-
ply switches internal to the DS1236 may not be large
enough to support the required load through V
CCO
with
a reasonable voltage drop. For these applications, the
PF and PF outputs are provided to gate external power
switching devices. As shown in Figure 9, power to the
load is switched from V
CC
to battery on power-down,
and from battery to V
CC
on power- up. The DS1336 is
designed to use the PF output to switch between V
BAT
and V
CC
. It provides better leakage and switchover per-
formance than currently available discrete components.
The transition threshold for PF and PF is set to the exter-
nal battery voltage V
BAT
, allowing a smooth transition
between sources. The load applied to the PF pin from
the external switch will be supplied by the battery.
Therefore, if a discrete switch is used, this load should
be taken into consideration when sizing the battery.
RESET CONTROL
As mentioned above, the DS1236 supports two modes
of operation. The CMOS mode is used when the system
incorporates a CMOS microprocessor which is battery
backed. The NMOS mode is used when a non-battery
backed processor is incorporated. The mode is se-
lected by the RC (Reset Control) pin. The level of this pin
distinguishes timing and level control on RST, RST, and
NMI outputs for volatile processor operation versus
nonvolatile battery backup or battery-operated proces-
sor applications.
相关PDF资料 |
PDF描述 |
|---|---|
| DS1238A | MicroManager(微管理器芯片) |
| DS1238 | MicroManager(微管理器芯片) |
| DS1239 | MicroManager Chip(微管理器芯片) |
| DS1250AB | 4096K Nonvolatile SRAM(4096K 非易失性静态RAM) |
| DS1250Y | 4096K Nonvolatile SRAM(4096K 非易失性静态RAM) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1236+5 | 功能描述:监控电路 RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| DS1236-10 | 功能描述:监控电路 RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| DS1236-10+ | 功能描述:监控电路 RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| DS1236-10N | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Power Supply Supervisor |
| DS1236-5 | 功能描述:监控电路 RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
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