参数资料
型号: DS1236
厂商: DALLAS SEMICONDUCTOR
元件分类: 电源管理
英文描述: MicroManager Chip(微管理器芯片)
中文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP16
封装: 0.300 INCH, DIP-16
文件页数: 3/19页
文件大小: 210K
代理商: DS1236
DS1236
022698 3/19
WATCHDOG TIMER
The DS1236 provides a watchdog timer function which
forces the RST and RST signals to the active state when
the strobe input (ST) is not stimulated for a predeter-
mined time period. This time period is 400 ms typically
with a maximum time-out of 600 ms. The watchdog
time-out period begins as soon as RST and RST are in-
active. If a high-to-low transition occurs at the ST input
prior to time-out, the watchdog timer is reset and begins
to time out again. The ST input timing is shown in
Figure 2. To guarantee the watchdog timer does not
time out, a high-to-low transition on ST must occur at or
less than 100 ms (minimum time-out) from a reset. If the
watchdog timer is allowed to time out, the RST and RST
outputs are driven to the active state for 25 ms mini-
mum. The ST input can be derived from microprocessor
address, data, and/or control signals. Under normal op-
erating conditions, these signals would routinely reset
the watchdog timer prior to time-out. If the watchdog tim-
er is not required, two methods have been provided to
disable it.
Permanently grounding the IN pin in the CMOS mode
(RC=1) will disable the watchdog. In normal operation
with RC=1, the watchdog is disabled as soon as the IN
pin is below V
TP
. With IN grounded, an NMI output will
occur only at power-up, or when the ST pin is strobed.
As shown in the Figure 3, a falling edge on ST will gener-
ate an NMI when IN is below V
TP
. This allows the pro-
cessor to verify that power is between V
TP
and V
CCTP
,
as an NMI will be returned immediately after the ST
strobe. The watchdog timer is not affected by the IN pin
when in NMOS mode (RC=0).
If the NMI signal is required to monitor supply voltages,
the watchdog may also be disabled by leaving the ST in-
put open. Independent of the state of the RC pin, the
watchdog is also disabled as soon as V
CC
falls to V
CCTP
.
PUSHBUTTON RESET
An input pin is provided on the DS1236 for direct con-
nection to a pushbutton. The pushbutton reset input re-
quires an active low signal. Internally, this input is pulled
high by a 10K resistor whenever V
CC
is greater than
V
BAT
. The PBRST pin is also debounced and timed such
that the RST and RST outputs are driven to the active
state for 25 ms minimum. This 25 ms delay begins as
the pushbutton is released from a low level. A typical ex-
ample of the power monitor, watchdog timer, and push-
button reset connections are shown in Figure 4. The
PBRST input is disabled whenever the IN pin voltage
level is less than V
TP
and the reset control (RC) is tied
high (CMOS mode). The PBRST input is also disabled
whenever V
CC
is below V
BAT
. Timing of the PBRST-gen-
erated RST is illustrated in Figure 5.
NON-MASKABLE INTERRUPT
The DS1236 generates a non-maskable interrupt NMI
for early warning of power failure to a microprocessor. A
precision comparator monitors the voltage level at the
IN pin relative to a reference generated by the internal
band gap. The IN pin is a high impedance input allowing
for a user-defined sense point. An external resistor volt-
age divider network (Figure 6) is used to interface with
high voltage signals. This sense point may be derived
from the regulated 5-volt supply or from a higher DC
voltage level closer to the main system power input.
Since the IN trip point V
TP
is 2.54 volts, the proper val-
ues for R1 and R2 can be determined by the equation as
shown in Figure 6. Proper operation of the DS1236 re-
quires that the voltage at the IN pin be limited to V
IN
.
Therefore, the maximum allowable voltage at the supply
being monitored (V
MAX
) can also be derived as shown
in Figure 6. A simple approach to solving this equation is
to select a value for R2 high enough to keep power con-
sumption low, and solve for R1. The flexibility of the IN
input pin allows for detection of power loss at the earliest
point in a power supply system, maximizing the amount
of time for microprocessor shut-down between NMI and
RST or RST.
When the supply being monitored decays to the voltage
sense point, the DS1236 pulses the NMI output to the
active state for a minimum of 200
μ
s. The NMI power fail
detection circuitry also has built-in time domain hystere-
sis. That is, the monitored supply is sampled periodical-
ly at a rate determined by an internal ring oscillator run-
ning at approximately 30 KHz (33
μ
s/cycle). Three
consecutive samplings of out-of-tolerance supply (be-
low V
SENSE
) must occur at the IN pin to activate NMI.
Therefore, the supply must be below the voltage sense
point for approximately 100
μ
s or the comparator will re-
set. In this way, power supply noise is removed from the
monitoring function, preventing false trips. During a
power-up , any IN pin levels below V
TP
are disabled
from reaching the NMI pin until V
CC
rises to V
CCTP
. As a
result, any potential NMI pulse will not be initiated until
V
CC
reaches V
CCTP
.
Removal of an active low level on the NMI pin is con-
trolled by either an internal time-out (when IN pin is less
than V
TP
) or by the subsequent rise of the IN pin above
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