参数资料
型号: DS1236A
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 电源管理
英文描述: MicroManager Chip(微管理器芯片)
中文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP16
封装: 0.300 INCH, DIP-16
文件页数: 19/19页
文件大小: 209K
代理商: DS1236A
DS1236A
022698 19/19
NOTES:
1. All voltages referenced to ground. A 0.1
μ
F capacitor is recommended between V
CC
and GND.
2. Measured with V
CCO
, CEO, PF, PF, ST, PBRST, RST, RST, and NMI pin open. I
BAT
specified at 25
°
C.
3. I
CCO1
is the maximum average load which the DS1236A can supply at V
CC
-0.3V through the V
CCO
pin during
normal 5-volt operation.
4. I
CCO2
is the maximum average load which the DS1236A can supply through the V
CCO
pin during data reten-
tion battery supply operation, with a maximum drop of 0.8 volts.
5. With t
R
= 5
μ
s.
6. V
CCO
is approximately V
BAT
-0.5V at 1
μ
A load.
7. Sleep mode is not invoked.
8. Sleep mode is invoked.
9. t
REC
is the minimum time required before CEI/CEO memory access is allowed.
10.t
CE
maximum must be met to ensure data integrity on power loss.
11. IN input is less than V
TP
but V
CC
greater than V
CCTP
.
12.All outputs except RST which is 25
μ
A maximum.
13.All outputs except RST and NMI, which is 25
μ
A minimum.
14.Pulse width of NMI requires that the IN pin remain below V
TP
. If the IN pin returns to a level above V
TP
for a
period longer than t
IPD
and before the t
NMI
period has elapsed, the NMI pin will immediately return to a high.
15.IN pin greater than V
TP
when V
CC
supply rises to V
BAT
. Example: IN tied to GND.
16.IN pin less than V
TP
when V
CC
supply rises to V
BAT
.
17.CEI low.
18.The WC/SC pin contains an internal latch which drives back on to the pin. This latch requires +200
μ
amps to
switch states. The ST pin will sink +50 uamps in normal operation and +1
μ
amp in the sleep mode.
19.If no battery is attached (i.e., V
BAT
=GND) then V
OHL
will track V
CC
.
20.ST should be active low before the watchdog is disabled (i.e., before the ST input is tristated).
TRI
+5V
ST
OUTPUT
3.3 K
2.2 K
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