参数资料
型号: DS1236A
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 电源管理
英文描述: MicroManager Chip(微管理器芯片)
中文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP16
封装: 0.300 INCH, DIP-16
文件页数: 2/19页
文件大小: 209K
代理商: DS1236A
DS1236A
022698 2/19
PIN DESCRIPTION
PIN NAME
DESCRIPTION
V
BAT
+3V battery input provides nonvolatile operation of control functions.
V
CCO
V
CC
output for nonvolatile SRAM applications.
V
CC
+5V primary power input.
PF
Power fail indicator, active high, used for external power switching as shown in NO TAG.
PF
Power fail indicator, active low.
WC/SC
Wake-up and Sleep control. Invokes low-power mode.
RC
Reset control input. Determines reset output . Normally low for NMOS processors and high for
battery-backed CMOS processors.
IN
Early warning power fail input. This voltage sense point can be tied (via resistor divider) to a
user-selected voltage.
NMI
Non-maskable interrupt. Used in conjunction with the IN pin to indicate an impending power
failure.
ST
Strobe input. A high-to-low transition will reset the watchdog timer, indicating that software is
still in control.
CEO
Chip enable output. Used with nonvolatile SRAM applications.
CEI
Chip enable input.
PBRST
Pushbutton reset input.
RST
Active low reset output.
RST
Active high reset output.
PROCESSOR MODE
A distinction is often made between CMOS and NMOS
processor systems. In a CMOS system, power con-
sumption may be a concern, and nonvolatile operation
is possible by battery backing both the SRAM and the
CMOS processor. All resources would be maintained in
the absence of V
CC
. A power-down reset is not issued
since the low-power mode of most CMOS processors
(Stop) is terminated with a Reset. A pulsed interrupt
(NMI) is issued to allow the CMOS processor to invoke a
sleep mode to save power. For this case, a power-on re-
set is desirable to wake up and initialize the processor.
The CMOS mode is invoked by connecting RC to V
CCO
.
An NMOS processor consumes more power, and con-
sequently may not be battery backed. In this case, it is
desirable to notify the processor of a power fail, then
keep it in reset during the loss of V
CC
. This avoids inter-
mittent or aberrant operation. On power-up, the proces-
sor will continue to be reset until V
CC
reaches an opera-
tional level to provide an orderly start. The NMOS mode
is invoked by connecting RC to ground.
POWER MONITOR
The DS1236A employs a band gap voltage reference
and a precision comparator to monitor the 5-volt supply
(V
CC
) in microprocessor-based systems. When an
out-of-tolerance condition occurs, the RST and RST
outputs are driven to the active state. Th e V
CC
trip point
(V
CCTP
) is set for 10% operation so that the RST and
RST outputs will become active as V
CC
falls below 4.5
volts (4.37 typical). The V
CCTP
for the 5% operation op-
tion (DS1236A–5) is set for 4.75 volts (4.62 typical). The
RST and RST signals are excellent for microprocessor
reset control, as processing is stopped at the last possi-
ble moment of in-tolerance V
CC
. On power-up, the RST
and RST signals are held active for a minimum of 25 ms
(100 ms typical) after V
CCTP
is reached to allow the
power supply and microprocessor to stabilize. Note:
The operation described above is obtained with the re-
set control pin (RC) connected to GND (NMOS mode).
Please review the reset control section for more infor-
mation.
相关PDF资料
PDF描述
DS1236 MicroManager Chip(微管理器芯片)
DS1238A MicroManager(微管理器芯片)
DS1238 MicroManager(微管理器芯片)
DS1239 MicroManager Chip(微管理器芯片)
DS1250AB 4096K Nonvolatile SRAM(4096K 非易失性静态RAM)
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