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参数资料
| 型号： | DS1250W |
| 厂商： | DALLAS SEMICONDUCTOR |
| 元件分类： | DRAM |
| 英文描述： | 3.3V 4096K Nonvolatile SRAM(3.3V 4096K 非易失性静态RAM) |
| 中文描述： | 512K X 8 NON-VOLATILE SRAM MODULE, 150 ns, DMA32 |
| 文件页数： | 2/11页 |
| 文件大小： | 108K |
| 代理商： | DS1250W |
DS1250W
022598 2/11
DESCRIPTION
The DS1250W 3.3V 4096K Nonvolatile SRAM is a
4,194,304–bit, fully static, nonvolatile SRAM organized
as 524,288 words by 8 bits. Each NV SRAM has a self–
contained lithium energy source and control circuitry
which constantly monitors V
CC
for an out–of–tolerance
condition. When such a condition occurs, the lithium en-
ergy source is automatically switched on and write pro-
tection is unconditionally enabled to prevent data cor-
ruption. DIP–package DS1250W devices can be used
in place of existing 512K x 8 static RAMs directly con-
forming to the popular bytewide 32–pin DIP standard.
DS1250W devices in the PowerCap Module package
are directly surface mountable and are normally paired
with a DS9034PC PowerCap to form a complete Non-
volatile SRAM module. There is no limit on the number
of write cycles that can be executed and no additional
support circuitry is required for microprocessor interfac-
ing.
READ MODE
The DS1250W executes a read cycle whenever WE
(Write Enable) is inactive (high) and CE (Chip Enable)
and OE (Output Enable) are active (low). The unique
address specified by the 19 address inputs (A
0
– A
18
)
defines which of the 524,288 bytes of data is to be ac-
cessed. Valid data will be available to the eight data out-
put drivers within t
ACC
(Access Time) after the last ad-
dress input signal is stable, providing that CE and OE
(Output Enable) access times are also satisfied. If OE
and CE access times are not satisfied, then data access
must be measured from the later occurring signal (CE or
OE) and the limiting parameter is either t
CO
for CE or t
OE
for OE rather than address access.
WRITE MODE
The DS1250W executes a write cycle whenever the WE
and CE signals are active (low) after address inputs are
stable. The later occurring falling edge of CE or WE will
determine the start of the write cycle. The write cycle is
terminated by the earlier rising edge of CE or WE. All
address inputs must be kept valid throughout the write
cycle. WE must return to the high state for a minimum
recovery time (t
WR
) before another cycle can be initi-
ated. The OE control signal should be kept inactive
(high) during write cycles to avoid bus contention. How-
ever, if the output drivers are enabled (CE and OE ac-
tive) then WE will disable the outputs in t
ODW
from its
falling edge.
DATA RETENTION MODE
The DS1250W provides full functional capability for V
CC
greater than 3.0 volts and write protects by
2.8 volts. Data is maintained in the absence of V
CC
with-
out any additional support circuitry. The nonvolatile
static RAMs constantly monitor V
CC
. Should the supply
voltage decay, the NV SRAMs automatically write pro-
tect themselves, all inputs become “don’t care,” and all
outputs become high impedance. As V
CC
falls below
approximately 2.5 volts, a power switching circuit con-
nects the lithium energy source to RAM to retain data.
During power–up, when V
CC
rises above approximately
2.5 volts, the power switching circuit connects external
V
CC
to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after V
CC
exceeds
3.0 volts.
FRESHNESS SEAL
Each DS1250W device is shipped from Dallas Semi-
conductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When V
CC
is first
applied at a level greater than 3.0 volts, the lithium ener-
gy source is enabled for battery back–up operation.
PACKAGES
The DS1250W is available in two packages: 32–pin DIP
and 34–pin PowerCap Module (PCM). The 32–pin DIP
integrates a lithium battery, an SRAM memory and a
nonvolatile control function into a single package with a
JEDEC–standard 600 mil DIP pinout. The 34–pin Pow-
erCap Module integrates SRAM memory and nonvola-
tile control into a module base along with contacts for
connection to the lithium battery in the DS9034PC Pow-
erCap. The PowerCap Module package design allows
a DS1250W PCM device to be surface mounted without
subjecting its lithium backup battery to destructive high–
temperature reflow soldering. After a DS1250W mod-
ule base is reflow soldered, a DS9034PC PowerCap is
snapped on top of the base to form a complete Nonvola-
tile SRAM module. The DS9034PC is keyed to prevent
improper attachment. DS1250W module bases and
DS9034PC PowerCaps are ordered separately and
shipped in separate containers. See the DS9034PC
data sheet for further information.
相关PDF资料 |
PDF描述 |
|---|---|
| DS1251Y | 4096K NV SRAM with Phantom Clock(带幻影时钟的4096K NV 静态RAM) |
| DS1258AB | 128K x 16 Nonvolatile SRAM(128K x 16 非易失性静态RAM) |
| DS1258Y | 128K x 16 Nonvolatile SRAM(128K x 16 非易失性静态RAM) |
| DS1258W | 3.3V 128K x 16 Nonvolatile SRAM(3.3V 128K x 16 非易失性静态RAM) |
| DS1259 | Battery Manager Chip(电池管理芯片) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1250W-100 | 功能描述:NVRAM 3.3V 4096K NV SRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1250W-100+ | 功能描述:NVRAM 3.3V 4096K NV SRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1250W-100IND | 功能描述:NVRAM 3.3V 4096K NV SRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1250W-100IND+ | 功能描述:NVRAM 3.3V 4096K NV SRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1250W-150 | 功能描述:NVRAM 3.3V 4096K NV SRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
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