参数资料
型号: DS1258AB-70#
厂商: Maxim Integrated
文件页数: 6/8页
文件大小: 0K
描述: IC NVSRAM 2MBIT 70NS 40DIP
标准包装: 9
格式 - 存储器: RAM
存储器类型: NVSRAM(非易失 SRAM)
存储容量: 2M (128K x 16)
速度: 70ns
接口: 并联
电源电压: 4.75 V ~ 5.25 V
工作温度: 0°C ~ 70°C
封装/外壳: 40-DIP 模块(0.610",15.495mm)
供应商设备封装: 40-EDIP
包装: 管件
DS1258Y/AB
POWER-DOWN/POWER-UP CONDITION
POWER-DOWN/POWER-UP TIMING
(t A : See Note 10)
CEU , CEL
PARAMETER
at V IH before Power-Down
SYMBOL
t PD
MIN
0
TYP
MAX
UNITS
m s
NOTES
11
V CC slew from V TP to 0V
V CC slew from 0V to V TP
t F
t R
300
300
m s
m s
CEU , CEL
at V IH after Power-Up
t REC
2
125
ms
(t A =+25 ° C)
PARAMETER
Expected Data Retention Time
SYMBOL
t DR
MIN
10
TYP
MAX
UNITS
years
NOTES
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1) WE is high for a Read Cycle.
2) OE = V IH or V IL . If OE = V IH during write cycle, the output buffers remain in a high impedance state.
3) t WP is specified as the logical AND of CEU or CEL and WE . t WP is measured from the latter of CEU ,
CEL or WE going low to the earlier of CEU , CEL or WE going high.
4) t DS is measured from the earlier of CEU or CEL or WE going high.
5) These parameters are sampled with a 5pF load and are not 100% tested.
6) If the CEU or CEL low transition occurs simultaneously with or later than the WE low transition in
the output buffers remain in a high impedance state during this period.
7) If the CEU or CEL high transition occurs prior to or simultaneously with the WE high transition, the
output buffers remain in high impedance state during this period.
6 of 8
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