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参数资料
| 型号： | DS1384 |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | XO, clock |
| 英文描述： | Watchdog Timekeeping Controller(看门狗计时器芯片) |
| 中文描述： | 1 TIMER(S), REAL TIME CLOCK, PQFP44 |
| 封装： | QFP-44 |
| 文件页数： | 3/15页 |
| 文件大小： | 130K |
| 代理商： | DS1384 |
DS1384
062598 3/15
SRAM location. When one of the on–chip 64 registers is
addressed, data will be written to the selected register
on the rising edge of WE.
INTA –
Interrupt Output A (output; active low): Interrupt
output A can be programmed as a Time of Day Alarm or
as a Watchdog Alarm (Interrupt output B becomes the
alternate function). In addition, INTA can be pro-
grammed to output either a pulse or a level.
INTB –
Interrupt Output B (output; active high or low):
Interrupt output B outputs the alarm (Time of Day or
Watchdog) that is not selected for INTA. Interrupt output
B is programmable high or low.
Both INTA and INTB(INTB) are open drain outputs. The
two interrupts and the internal clock continue to run
regardless of the level of V
CC
. However, it is important
to insure that the pull–up resistors used with the inter-
rupt pins are never pulled up to a value which is greater
than V
CC
+ 0.3V. As V
CC
falls below approximately
3.0 volts, a power switching circuit turns the lithium
energy source on the maintain the clock, and timer data
functionality. It is also required to insure that during this
time (battery backup mode), the voltage present at INTA
and INTB(INTB) does never exceed V
bat
. At all times
the current on each should not exceed +2.1 mA or
–1.0 mA.
X1, X2 –
Crystal inputs: Connections for a standard
32.768 KHz quartz crystal. When ordering, request a
load capacitance or 6 pF. The internal oscillator circuitry
is designed for operation with a crystal having a speci-
fied load capacitance (C
L
) of 6 pF.
For more information on crystal selection and crystal
layout considerations, please consult Application Note
58, “Crystal Considerations with Dallas Real Time
Clocks”.
SQW –
Square Wave (output): This pin can be pro-
grammed to output a 1024 Hz square wave signal.
When the signal is turned off, the pin is high Z.
PFO –
Power Fail Signal (output; active low when V
WP
occurs): High state occurs t
REC
after power–up and
V
CC
>4.5 volts.
ADDRESS DECODING
The DS1384 accommodates 17 address lines which al-
lows direct connection of up to 128K bytes of static
RAM. The lower 14 bytes of RAM, regardless of the
density used, will always contain the timekeeping,
alarm, and watchdog registers. The 14 clock registers
reside in the lower 14 RAM locations without conflict by
inhibiting the OER (output enable RAM) signal during
clock access. Since the watchdog timekeeping chip ac-
tually contains 64 registers (14 RTC and 50 user RAM),
the lower 64 bytes of any attached memory resides with-
in the DS1384. However, the RAM’s physical location is
transparent to the user and the memory map looks con-
tinuous from the first clock address to the upper most at-
tached RAM address.
OPERATION – READ CYCLE
The DS1384 executes a read cycle whenever WE is
inactive (high) and CE and OE are active (low). The
unique address specified by the address inputs
(A0–A16) defines which of the on–chip 64 RTC/RAM or
external SRAM locations is to be accessed.
When the address value presented to the DS1384 is in
the range of 00000H through 0003FH, one of the 64 on–
chip registers will be selected and valid data will be
available to the eight data output drivers within t
ACC
(access time) after the address input signal is stable,
providing that the CE and OE access times are also
satisfied. If they are not, then data access must be mea-
sured from the latter occurring signal (CE or OE) and the
limiting parameter is either t
CO
for CE or t
OE
for OE
rather than the address access time. When one of the
on–chip registers is selected for read, the OER signal
will remain inactive throughout the read cycle.
When the address value presented to the DS1384 is in
the range of 00040H through 1FFFFH, an external
SRAM location will be selected. In this case the OE sig-
nal will be passed to the OER pin, with the specified
delay times of t
AOEL
or t
OERL
.
OPERATION – WRITE CYCLE
The DS1384 is in the write mode whenever the WE
(Write Enable) and CE (Chip Enable) signals are in the
active (low) state after the address inputs are stable.
The latter occurring falling edge of CE or WE will deter-
mine the start of the write cycle. The write cycle is termi-
nated by the earlier rising edge of CE or WE. All address
inputs must be kept valid throughout the write cycle. WE
must return to the high state for a minimum recovery
state (t
WR
) before another cycle can be initiated. Data
must be valid on the data bus with sufficient Data Set Up
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相关代理商/技术参数 |
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| DS1384FP | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Watchdog Timekeeping Controller |
| DS1384FP-12 | 功能描述:IC CTRLR RTC WDOG 120NS 44-MQFP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 实时时钟 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- 类型:时钟/日历 特点:警报器，闰年，SRAM 存储容量:- 时间格式:HH:MM:SS（12/24 小时） 数据格式:YY-MM-DD-dd 接口:SPI 电源电压:2 V ~ 5.5 V 电压 - 电源，电池:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WDFN 裸露焊盘 供应商设备封装:8-TDFN EP 包装:管件 |
| DS1384FP-12+ | 功能描述:实时时钟 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
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