DS1384
062598 7/15
TIME OF DAY ALARM MASK BITS
Figure 3
MINUTES
HOURS
DAYS
1
0
ALARM ONCE PER MINUTE
ALARM WHEN MINUTES MATCH
ALARM WHEN HOURS AND MINUTES MATCH
ALARM WHEN HOURS, MINUTES,
AND DAYS MATCH
1
1
1
1
1
0
0
0
0
0
NOTE: ANY OTHER BIT COMBINATIONS OF MASK BIT SETTINGS PRODUCE ILLOGICAL OPERATION.
REGISTER
TIME OF DAY REGISTERS
Registers 0, 1, 2, 4, 6, 8, 9 and A contain time of day data
in BCD. Ten bits within these eight registers are not
used and will always read zero regardless of how they
are written. Bits 6 and 7 in the Months Register (9) are
binary bits.
When set to logical zero, EOSC (bit 7) enables the real–
time clock oscillator. This bit will normally be turned on
by the user during device initialization. However, the os-
cillator can be turned on and off as necessary by setting
this bit to the appropriate level.
Bit 6 of this same byte controls the square wave output
(pin 24). When set to logical zero, the square wave out-
put pin will output a 1024 Hz square wave signal. When
set to logic one the square wave output pin is in a high
impedance state.
Bit 6 of the Hours Register is defined as the 12– or
24–Hour Select Bit. When set to logic one, the 12–hour
format is selected. In the 12–hour format, bit 5 is the AM/
PM bit with logical one being PM. In the 24–hour mode,
bit 5 is the second 10–hour bit (20–23 hours). The time
of day registers are updated every 0.01 seconds from
the real time clock, except when the TE bit (bit 7 of regis-
ter B) is set low or the clock oscillator is not running.
The preferred method of synchronizing data access to
and from the Watchdog Timekeeper is to access the
Command Register by doing a write cycle to address lo-
cation 0B and setting the TE bit (Transfer Enable bit) to a
logic zero. This will freeze the external time of day regis-
ters at the present recorded time allowing access to oc-
cur without danger of simultaneous update. When the
watch registers have been read or written a second
write cycle to location 0B, setting the TE bit to a logic
one, will put the time of day registers back to being up-
dated every 0.01 second. No time is lost in the real time
clock because the internal copy of the time of day regis-
ter buffers are continually incremented while the exter-
nal memory registers are frozen. An alternate method of
reading and writing the time of day registers is to ignore
synchronization. However, any single read may give er-
roneous data as the real time clock may be in the pro-
cess of updating the external memory registers as data
is being read.
The internal copies of seconds through years are in-
cremented and Time of Day Alarm is checked during the
period that hundredths of seconds reads 99 and are
transferred to the external register when hundredths of
seconds roll from 99 to 00. A way of making sure data is
valid is to do multiple reads and compare. Writing the
registers can also produce erroneous results for the
same reasons. A way of making sure that the write cycle
has caused proper update is to do read verifies and re-
execute the write cycle if data is not correct. While the
possibility of erroneous results from reads and write
cycles has been stated, it is worth noting that the proba-
bility of an incorrect result is kept to a minimum due to
the redundant structure of the Watchdog Timekeeper.
TIME OF DAY ALARM REGISTERS
Registers 3, 5, and 7 contain the time of day alarm regis-
ters. Bits 3, 4, 5, and 6 of register 7 will always read zero
regardless of how they are written. Bit 7 of registers 3, 5,
and 7 are mask bits (Figure 3). When all of the mask bits
are logical zero, a time of day alarm will only occur when
registers 2, 4, and 6 match the values stored in registers
3, 5, and 7. An alarm will be generated every day when
bit 7 of register 7 is set to a logical one. Similarly, an
alarm is generated every hour when bit 7 of registers 7