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参数资料
| 型号： | DS1384 |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | XO, clock |
| 英文描述： | Watchdog Timekeeping Controller(看门狗计时器芯片) |
| 中文描述： | 1 TIMER(S), REAL TIME CLOCK, PQFP44 |
| 封装： | QFP-44 |
| 文件页数： | 8/15页 |
| 文件大小： | 130K |
| 代理商： | DS1384 |
DS1384
062598 8/15
and 5 is set to a logical 1. When bit 7 of registers 7, 5,
and 3 is set to a logical 1, an alarm will occur every min-
ute when register 1 (seconds) rolls from 59 to 00.
Time of day alarm registers are written and read in the
same format as the time of day registers. The time of
day alarm flag and interrupt is always cleared when
alarm registers are read or written.
WATCHDOG ALARM REGISTERS
Registers C and D contain the time for the Watchdog
Alarm. The two registers contain a time count from
00.01 to 99.99 seconds in BCD. The value written into
the Watchdog Alarm Registers can be written or read in
any order. Any access to Register C or D will cause the
Watchdog Alarm to reinitialize and clears the Watchdog
Flag Bit and the Watchdog Interrupt Output. When a
new value is entered or the Watchdog Registers are
read, the Watchdog Timer will start counting down from
the entered value to zero. When zero is reached, the
Watchdog Interrupt Output will go to the active state.
The Watchdog Timer Countdown is interrupted and re-
initialized back to the entered value every time either of
the registers are accessed. In this manner, controlled
periodic accesses to the Watchdog Timer can prevent
the Watchdog Alarm from ever going to an active level.
If access does not occur, countdown alarm will be repet-
itive. The Watchdog Alarm Registers always read the
entered value. The actual count down register is inter-
nal and is not readable. Writing registers C and D to zero
will disable the Watchdog Alarm feature.
COMMAND REGISTER
Address location 0Bh is the Command Register where
mask bits, control bits and flag bits reside. The opera-
tion of each bit is as follows:
TE –
Bit 7 Transfer enable – This bit when set to a logic 0
will disable the transfer of data between internal and ex-
ternal clock registers. The contents in the external clock
registers are now frozen and reads or writes will not be
affected with updates. This bit must be set to a logic 1 to
allow updates.
IPSW –
Bit 6 Interrupt switch – When set to a logic 1,
INTA is the Time of Day Alarm and INTB/(INTB) is the
Watchdog Alarm. When set to logic 0, this bit reverses
the output pins. INTA is now the Watchdog Alarm output
and INTB/(INTB) is the Time of Day Alarm output.
IBH/LO –
Bit 5 Interrupt B Sink or Source Current -
When this bit is set to a logic 1 and V
CC
is applied,
INTB/(INTB) will source current (see DC characteristics
I
OH
). When this bit is set to a logic 0, INTB will sink cur-
rent (see DC characteristics I
OL
).
PU/LVL –
Bit 4 Interrupt pulse mode or level mode - This
bit determines whether both interrupts will output a
pulse or level signal. When set to a logic 0, INTA and
INTB/(INTB) will be in the level mode. When this bit is
set to a logic 1, the pulse mode is selected and INTA will
sink current for a minimum of 3 ms and then release.
INTB/(INTB) will either sink or source current, depend-
ing on the condition of bit 5, for a minimum of 3 ms and
then release.
WAM –
Bit 3 Watchdog Alarm Mask – When this bit is set
to a logic 0, the Watchdog Interrupt output will be acti-
vated. The activated state is determined by bits 1,4,5,
and 6 of the Command Register. When this bit is set to a
logic 1, the Watchdog interrupt output is deactivated.
TDM –
Bit 2 Time of Day Alarm Mask – When this bit is
set to a logic 0, the Time of Day Alarm Interrupt output
will be activated. The activated state is determined by
bits 0,4,5, and 6 of the Command Register. When this
bit is set to a logic 1 , the Time of Day Alarm interrupt out-
put is deactivated.
WAF –
Bit 1 Watchdog Alarm Flag – This bit is set to a
logic 1 when a watchdog alarm interrupt occurs. This bit
is read only.
The bit is reset when any of the Watchdog Alarm regis-
ters are accessed.
When the interrupt is in the pulse mode (see bit 4 defini-
tion), this flag will be in the logic 1 state only during the
time the interrupt is active.
TDF –
Bit 0 Time of Day Flag – This is a read only bit.
This bit is set to a logic 1 when a time of day alarm has
occurred. The time the alarm occurred can be deter-
mined by reading the Time of Day Alarm registers. This
bit is reset to a logic 0 state when any of the Time of Day
Alarm registers are accessed.
When the interrupt is in the pulse mode (see bit 4 defini-
tion), this flag will be in the logic 1 state only during the
time the interrupt is active.
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相关代理商/技术参数 |
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| DS1384FP | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Watchdog Timekeeping Controller |
| DS1384FP-12 | 功能描述:IC CTRLR RTC WDOG 120NS 44-MQFP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 实时时钟 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- 类型:时钟/日历 特点:警报器，闰年，SRAM 存储容量:- 时间格式:HH:MM:SS（12/24 小时） 数据格式:YY-MM-DD-dd 接口:SPI 电源电压:2 V ~ 5.5 V 电压 - 电源，电池:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WDFN 裸露焊盘 供应商设备封装:8-TDFN EP 包装:管件 |
| DS1384FP-12+ | 功能描述:实时时钟 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
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