参数资料
型号: DS1856B-M50+
厂商: Maxim Integrated Products
文件页数: 4/31页
文件大小: 0K
描述: IC DGTL POT 50K 256TAPS 16CSBGA
产品培训模块: Obsolescence Mitigation Program
标准包装: 100
接片: 256
电阻(欧姆): 50k
电路数: 2
温度系数: 标准值 50 ppm/°C
存储器类型: 非易失
接口: 2 线串口
电源电压: 2.85 V ~ 5.5 V
工作温度: -40°C ~ 95°C
安装类型: 表面贴装
封装/外壳: 16-LBGA,CSPBGA
供应商设备封装: 16-CSBGA(4x4)
包装: 托盘
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
12
Maxim Integrated
DS1856
memories can be accessed by two separate 2-wire
slave addresses (see Table 4). The Main Device
address is A2h (or determined by the value in Table 03,
byte 8Ch, when ADFIX = 1) and the Auxiliary Device
address is A0h (fixed). A configuration bit, ADEN
(Table 03, byte 89h, bit 5), determines whether the
DS1856 uses one or two 2-wire slave addresses. This
feature can be used to save component count in SFF
applications or other applications where both GBIC
and monitoring functions are implemented and two
device addresses are needed.
The memory organization for ADEN = 0 is shown in
Figure 2. In this configuration, the 128 bytes of
Auxiliary Device EEPROM are located at memory loca-
tions 00h to 7Fh and accessed using the Auxiliary
Device 2-wire slave address of A0h (fixed). The
remainder of the DS1856’s memory is accessed using
the Main Device address.
The memory organization of the second configuration,
ADEN = 1, is shown in Figure 3. In this configuration, all
of the DS1856’s memory including the Auxiliary memo-
ry is accessed using only the Main Device address.
The Auxiliary Device memory is mapped into Table 00
and Table 01 in the Main Device. Both tables map to
the same block of physical memory. This is done to
improve the compatibility between previous members
of this IC family such as the DS1858/DS1859 and the
DS1852. In this configuration, the DS1856 ignores com-
munication using the Auxiliary Device address.
The value of the Main Device address can be changed
to a value other than the default value of A2h (see data
sheet Table 5). There can be up to 128 devices sharing
a common 2-wire bus, with each device having its own
unique address. To change the Main Device address,
first write the desired value to the Chip Address byte
(Table 03, byte 8Ch). Then, enable the new address by
setting ADFIX to a 1. Subsequent 2-wire communica-
tion must be performed using the new Main Device
address. When ADFIX = 0, the Chip Address byte is
ignored, and the Main Device address is set to A2h.
TABLE 00h/01h
EEPROM
AUXILIARY MEMORY
(128 BYTES)
80h
FFh
255
FF
127
7F
128
80
183
B7
199
C7
200
C8
LOWER MEMORY
TABLE SELECT BYTE
PASSWORD ENTRY
(PWE) (4 BYTES)
00h
7Fh
2-WIRE ADDRRESS A2h (DEFAULT)
NOTE 1: ADEN BIT = 1. ALL MEMORY (INCLUDING THE AUXILIARY MEMORY) IS ADDRESSED USING THE
NOTE 1: MAIN DEVICE 2-WIRE SLAVE ADDRESS.
NOTE 2: TABLES 00h AND 01h ACCESS THE SAME PHYSICAL MEMORY.
NOTE 3: TABLE 02h DOES NOT EXIST.
DEC HEX
00
TABLE 03h
CONFIGURATION
TABLE
80h
B7h
TABLE 04h
RESISTOR 0
LOOK-UP TABLE
(72 BYTES)
80h
C7h
TABLE 05h
RESISTOR 1
LOOK-UP TABLE
(72 BYTES)
80h
C7h
RESERVED AND
CALIBRATION
CONSTANTS
RESERVED AND
CALIBRATION
CONSTANTS
F0h
FFh
F0h
FFh
Figure 3. Memory Organization, ADEN = 1
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