参数资料
| 型号： | DS1862B+T&R |
| 厂商： | Maxim Integrated |
| 文件页数： | 23/43页 |
| 文件大小： | 0K |
| 描述： | IC LASR CTRLR 7CHAN 5.5V 25CSBGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 激光二极管控制器（光纤） |
| 数据速率： | 10Gbps |
| 通道数： | 7 |
| 电源电压： | 2.9 V ~ 5.5 V |
| 电流 - 电源： | 3mA |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 25-TFBGA，CSPBGA |
| 供应商设备封装： | 25-BGA（5x5） |
| 包装： | 带卷 (TR) |
| 安装类型： | 表面贴装 |
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XFP Laser Control and Digital Diagnostic IC
SHUTDOWN LOGIC
LATCHED-TX-FAULT
BMD (PIN)
(TX-P CURRENT)
ADC
THRESHOLD
LOW TX-P MASK
QT LOW
TX-P FLAG
BMD (PIN)
(TX-P CURRENT)
ADC
QT HIGH
TX-P FLAG
FETG_POL
FETG (PIN)
THRESHOLD
HIGH TX-P MASK
BIASSET (PIN)
(BIASSET CURRENT)
ADC
QT HIGH
BIAS FLAG
0
FETG_POL
DRIVE A P-CHANNEL SWITCH
THRESHOLD
HIGH BIAS MASK
1
DRIVE A N-CHANNEL SWITCH
SOFT TX-D
P-DOWN/RST (PIN)
QT LOW TX-P FLAG
TX-D (PIN)
SAFETY FLAG
SHUTDOWN
FLAG
QT HIGH TX-P FLAG
QT HIGH BIAS FLAG
SAFETY FLAG
SOFT P-DOWN/RST
Figure 12. Safety Fault and Shutdown Logic
The polarity of the FETG pin can also be reversed by
setting the FETG_POL bit. Once a safety fault has
occurred, the FETG pin and all of the attendant flags can
only be reset by pulsing the P-DOWN/RST pin high for the
reset time, t RESET , or by toggling the SOFT P-DOWN/RST
bit in Byte 6Eh, bit 3. See the Power-Down/Reset Pin sec-
tion for more details.
Power-Down/Reset Pin
The P-DOWN/RST pin is a multifunction input pin that
resets and/or powers down the DS1862. Since the pin is
internally pulled up, its normal state is released, which
corresponds to power-down mode. If the P-DOWN/RST
pin is released, or driven high, the DS1862 responds by
shutting down the MODSET and BIASSET currents.
Once the pin is pulled low, operation continues (if not
inhibited by a safety fault). Besides powering down the
DS1862, a high-going pulse with minimum reset time,
t RESET , can be applied to the P-DOWN/RST pin. This is
necessary to restart the DS1862, especially if it is in a
safety shutdown condition and needs to be restarted
after the safety condition has been rectified. See the
timing diagrams for proper pin timing.
Power-Down Functionality
During power-down mode I BIASSET and I MODSET drop
below 10μA, effectively shutting down the laser. FETG
is not asserted and safety faults do not occur during
this period. During power-down, I 2 C communication is
still active, but the signal conditioner pins EN1 and EN2
are noncontrollable and automatically change to the
states: EN1 = 1 and EN2 = 0. Other internal flags/sig-
nals that are based on the signal conditioner inputs still
reflect the status on the signal conditioner pins during
power-down. For example, RX-LOS still reflects the sta-
tus of SC-RX-LOS, and MOD-NR still reflects the logical
states for the signal conditioner pins. Similarly, it is possi-
ble for FETG to be asserted, even though the BIASSET
and MODSET currents are shut down. However, during
power-down and a short period, t PDR-OFF , during power-
up, TX-P Low flag is ignored (internally automatically
masked out) and does not contribute to FETG’s logic.
____________________________________________________________________
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