参数资料
| 型号： | DS1862B+T&R |
| 厂商： | Maxim Integrated |
| 文件页数： | 39/43页 |
| 文件大小： | 0K |
| 描述： | IC LASR CTRLR 7CHAN 5.5V 25CSBGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 激光二极管控制器（光纤） |
| 数据速率： | 10Gbps |
| 通道数： | 7 |
| 电源电压： | 2.9 V ~ 5.5 V |
| 电流 - 电源： | 3mA |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 25-TFBGA，CSPBGA |
| 供应商设备封装： | 25-BGA（5x5） |
| 包装： | 带卷 (TR) |
| 安装类型： | 表面贴装 |
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XFP Laser Control and Digital Diagnostic IC
COMMUNICATIONS KEY
S
START
A
ACK
WHITE BOXES INDICATE THE MASTER IS
CONTROLLING SDA
NOTE:
ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST.
P
STOP
N
NOT
ACK
SHADED BOXES INDICATE THE SLAVE IS
CONTROLLING SDA
THE FIRST BYTE SENT AFTER A START CONDITION IS
ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE
SR
REPEATED
START
X
X
X
X
X
X
X
X
8-BIT ADDRESS OR DATA
READ/WRITE BIT.
WRITE A SINGLE BYTE
S
1 0
1
0 0
0
0
0
A
MEMORY ADDRESS
A
DATA
A
P
WRITE UP TO A 4-BYTE PAGE WITH A SINGLE TRANSACTION
S
1 0
1
0 0
0
0
0
A
MEMORY ADDRESS
A
DATA
A
DATA
A
P
READ A SINGLE BYTE WITH A DUMMY WRITE CYCLE TO SET THE ADDRESS COUNTER
S
1 0
1
0 0
0
0
0
A
MEMORY ADDRESS
A
SR
1 0
1
0 0
0
0
0
A
DATA
N
P
READ MULTIPLE BYTES WITH A DUMMY WRITE CYCLE TO SET THE ADDRESS COUNTER
S
1 0
1
0 0
0
0
0
A
MEMORY ADDRESS
A
SR
1 0
1
0 0
0
0
0
A
DATA
A
DATA
A
DATA
A
DATA
N
P
Figure 15. I 2 C Communications Examples
I 2 C Operation Using
Packet Error Checking
Read Operation with
Packet Error Checking
Packet error checking during reads is supported by the
DS1862. Information is transferred form the DS1862 in
much the same way as conventional I 2 C protocol, how-
ever, an extra CRC field is added and checked. The
master still begins by sending the device address (A0h
for DS1862), then the index pointer to the memory
address of interest. The next byte transferred, however,
is the value of the intended number of bytes to be read.
The calculation of the CRC-8 includes and requires the
explicit starting memory address to be included as the
second transferred byte (dummy write byte). Next, the
slave transfers the data back as the master acknowl-
edges. Only 1 to 128 bytes can be sequentially read
during one transmission while using PEC. After the
master reads the intended number of bytes, the CRC-8
value is transmitted by the DS1862. The master ends
the communication with a NACK and a STOP. See
Figure 16 for a graphical representation. The CRC-8 is
calculated starting with the MSB of the memory
address pointer, number of bytes to read, and the read
data. The master can then verify the CRC-8 value and
reject the read data if the CRC-8 value does not corre-
spond to the received CRC value. The CRC-8 must be
calculated by using the following polynomial for both
reads and writes:
C(x) = X 8 +X 2 + X + 1
Write Operation with
Packet Error Checking
Packet error checking during writes is also supported
by the DS1862. Information is written to the DS1862 in
much the same way as conventional I 2 C protocol, how-
ever, an extra CRC field is added and checked. The
master still begins by sending the device address, then
the index pointer to the memory address of interest.
The next byte, however, is the value of the intended
number of bytes to be written. The calculation of the
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