参数资料
| 型号： | DS1862B+T&R |
| 厂商： | Maxim Integrated |
| 文件页数： | 33/43页 |
| 文件大小： | 0K |
| 描述： | IC LASR CTRLR 7CHAN 5.5V 25CSBGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 激光二极管控制器（光纤） |
| 数据速率： | 10Gbps |
| 通道数： | 7 |
| 电源电压： | 2.9 V ~ 5.5 V |
| 电流 - 电源： | 3mA |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 25-TFBGA，CSPBGA |
| 供应商设备封装： | 25-BGA（5x5） |
| 包装： | 带卷 (TR) |
| 安装类型： | 表面贴装 |
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XFP Laser Control and Digital Diagnostic IC
85h
? APC REF FINE .................<R-Module/W-Module><Shadowed Nonvolatile><00> This 2-bit value in <1:0> sets
the fine APC current on BMD. The MSB is bit 1.
86h
? LUT RANGE .....................<R-Module/W-Module><Shadowed Nonvolatile><00> This 3-bit register in <2:0>
sets the current range on MODSET. The MSB is bit 2.
87h
? Control Register 1 ............<R-Module/W-Module><Shadowed Nonvolatile><00>
Bit 0: Reserved.
Bit 1: SRC_SINK_B. If set, then BMD sources current; otherwise, BMD sinks current.
Bit 2: Reserved.
Bit 3: Reserved.
Bit 4: QT TX-P LO Mask. If set, then TX-P low does not have the ability to cause a safety fault.
Bit 5: QT HIGH BIAS Mask. If set, then HIGH BIAS does not have the ability to cause a safety fault.
Bit 6: QT TX-P HI Mask. If set, then TX-P high does not have the ability to cause a safety fault.
Bit 7: FETG_POL. If set, then FETG asserts with a high logic level; otherwise, it asserts with a low logic level.
88h
? QT TX-P HI .......................<R-Module/W-Module><Shadowed Nonvolatile><FF> This is the TX-P quick-trip
threshold setting that is used as a comparison to generate a TX-P high safety fault.
89h
? QT TX-P LO ......................<R-Module/W-Module><Shadowed Nonvolatile><00> This is the TX-P quick-trip
threshold setting that is used as a comparison to generate a TX-P low safety fault.
8Ah
? QT HIGH BIAS .................<R-Module/W-Module><Shadowed Nonvolatile><FF> This is the TX-P quick-trip
threshold setting that is used as a comparison to generate a HIGH BIAS safety fault.
8Bh
? Control Register 2 ............<R-Module/W-Module><Shadowed Nonvolatile><00>
Bit 0: Reserved.
Bit 1: Reserved.
Bit 2: Reserved.
Bit 3: Reserved.
Bit 4: TEMP_INT/EXT. If set, then the LUT INDEX POINTER register is controlled by AUX2MON. Otherwise, the
internal temperature sensor controls the LUT.
Bit 5: Reserve_EN. If set, then V CC2/3 is actively updated in the monitor loop.
Bit 6: Reserved.
Bit 7: Reserved.
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