参数资料
型号: DS1863E+
厂商: Maxim Integrated
文件页数: 10/62页
文件大小: 0K
描述: IC LASR CTRLR 1CHAN 5.5V 16TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 96
类型: 激光二极管控制器
通道数: 1
电源电压: 2.85 V ~ 5.5 V
电流 - 电源: 5mA
电流 - 偏置: 1.2mA
工作温度: -40°C ~ 95°C
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 管件
安装类型: 表面贴装
产品目录页面: 1429 (CN2011-ZH PDF)
Burst-Mode PON Controller
With Integrated Monitoring
during start-up. Masking the alarms until the completion
of the binary search prevents false alarms.
I STEP is programmed by the customer using the Start-
up Step register. This value should be programmed to
the maximum safe current increase that is allowable
during start-up. If this value is programmed too low, the
DS1863 will still operate, but it could take significantly
longer for the algorithm to converge and hence to con-
trol the average power.
If a fault is detected, and TX-D is toggled to re-enable the
outputs, the DS1863 will power up following a similar
sequence to an initial power up. The only difference is
that the DS1863 already has determined the present tem-
perature, so the t INIT time is not required for the DS1863
to recall the APC and MOD set points from EEPROM.
internal APC and BIAS reference. The HTXP/LTXP com-
parison will check HTXP if the last bias-update compar-
ison was above the APC set-point, and LTXP if the last
bias update comparison was below the APC set-point.
The DS1863 has a programmable comparator sample
time based on an internally generated clock to facilitate a
wide variety of external filtering options suitable for burst
mode transmitter data rates between 155Mbits/s and
1250Mbits/s. The rising edge of burst enable (BEN) trig-
gers the sample to occur, and the Sample Rate register
determines the delay. The internal clock is asynchronous
to BEN, causing a 100ns uncertainty as to when the first
sample will occur following BEN. After the first sample
occurs, subsequent samples will occur on a regular
interval. The following sample rate options are available.
BIAS and MOD Output as a Function
of Transmit Disable (TX-D)
If TX-D is asserted (logic 1) during operation, the out-
puts will immediately turn off (t OFF ). When TX-D is
deasserted (logic 0), the DS1863 will turn on the MOD
output with the value associated with the present tem-
perature, and initialize the I BIAS using the same search
algorithm as done at start-up. Soft TX-D (Lower
Memory, Register 6Eh) when asserted would allow a
software control identical to the TX-D pin.
TX-D TIMING (NORMAL OPERATION)
TX-D
SR 3 – SR 0
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
MINIMUM TIME
FROM BEN TO FIRST
SAMPLE (t FIRST )
±50ns
350ns
550ns
750ns
950ns
1350ns
1550ns
1750ns
2150ns
2950ns
REPEATED SAMPLE
PERIOD FOLLOWING
FIRST SAMPLE (t REP )
800ns
1200ns
1600ns
2000ns
2800ns
3200ns
3600ns
4400ns
6000ns
I BIAS
t OFF
t ON
1001b*
3150ns
6400ns
I MOD
t OFF
t ON
* All codes greater than 1001b (1010b–111b) use the maximum
sample time of code 1001b.
Figure 2. TX-D Timing (Output Disabled During Normal Operating
Conditions).
APC/Quick-Trip Shared Comparator Timing
The DS1863 ’ s input comparator is shared between the
APC control loop and the three quick-trip alarms
(HTXP, LTXP and HBIAS). The comparator polls the
alarms in a round-robin multiplexed sequence. Six of
every eight of the comparator readings will be used for
APC Loop bias current control. The other two updates
will be used to check the HTXP/LTXP (Monitor Diode
voltage) and the HBIAS (MON1) signals against the
Comparisons of the HTXP, LTXP, and HBIAS quick-trip
alarms will not occur during the burst enable low time.
Any quick-trip alarm that is detected will by default
remain active until a subsequent comparator sample
shows the condition no longer exists.
A second bias current monitor compares the DS1863 ’ s
bias current DAC ’ s code to a digital value stored in the
MAX IBIAS register. This comparison is made every
bias current update to ensure that a high bias current
will be quickly detected.
10
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