参数资料
型号: DS1863E+
厂商: Maxim Integrated
文件页数: 4/62页
文件大小: 0K
描述: IC LASR CTRLR 1CHAN 5.5V 16TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 96
类型: 激光二极管控制器
通道数: 1
电源电压: 2.85 V ~ 5.5 V
电流 - 电源: 5mA
电流 - 偏置: 1.2mA
工作温度: -40°C ~ 95°C
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 管件
安装类型: 表面贴装
产品目录页面: 1429 (CN2011-ZH PDF)
Burst-Mode PON Controller
With Integrated Monitoring
I 2 C AC ELECTRICAL CHARACTERISTICS
(V CC = +2.85V to +3.9V, T A = -40°C to +95°C, unless otherwise noted, see Figure 9.)
PARAMETER
SCL Clock Frequency
SYMBOL
f SCL
(Note 12)
CONDITIONS
MIN
0
TYP
MAX
400
UNITS
kHz
Clock Pulse-Width Low
Clock Pulse-Width High
Bus Free Time Between STOP and
START Condition
START Hold Time
START Setup Time
t LOW
t HIGH
t BUF
t HD:STA
t SU:STA
1.3
0.6
1.3
0.6
0.6
μs
μs
μs
μs
μs
Data-In Hold Time
Data-In Setup Time
t HD:DAT
t SU:DAT
0
100
0.9
μs
ns
Rise Time of Both SDA and
SCL Signals
Fall Time of Both SDA and
SCL Signals
STOP Setup Time
Capacitive Load for Each Bus Line
EEPROM Write Time
t R
t F
t SU:STO
C B
t W
(Note 13)
(Note 13)
(Note 13)
(Note 14)
20 + 0.1C B
20 + 0.1C B
0.6
300
300
400
20
ns
ns
μs
pF
ms
NONVOLATILE MEMORY CHARACTERISTICS
(V CC = +2.85V to +3.9V, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EEPROM Write Cycles
+70°C
50,000
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
All voltages are referenced to ground. Currents into the IC are positive and out of the IC are negative.
Digital Inputs are at rail. FETG is disconnected SDA = SCL = 1.
See the Safety Shutdown (FETG) Output section for details.
Eight ranges allow the full-scale range to change from 625mV to 2.5V.
This specification applies to the expected full-scale value for the selected range. See the Comp Ranging byte for available
full-scale ranges.
Eight ranges allow the full-scale range to change from 312.5mV to 1.25V.
The output impedance of the DS1863 is proportional to its scale setting. For instance, if using the 1/2 scale, the output
impedance would be 1.5k Ω .
This specification applies to the expected full-scale value for the selected range. See the Mod Ranging byte for available
full-scale ranges.
See the APC/Quick-Trip Sample Timing section for details.
Assuming an appropriate initial step is programmed that would cause the power to exceed the APC set point within 4
steps, the bias current will be within 1% within the time specified by the binary search time.
Guaranteed by design.
I 2 C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I 2 C stan-
dard-mode timing.
C B —total capacitance of one bus line in picofarads.
EEPROM write begins after a STOP condition occurs.
4
_____________________________________________________________________
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