参数资料
型号: DS1865T+
厂商: Maxim Integrated Products
文件页数: 45/67页
文件大小: 0K
描述: IC PON TRIPLEXER CTRLR 28TQFN-EP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
系列: *
类型: *
应用: *
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 管件
DS1865
I2C AC ELECTRICAL CHARACTERISTICS
(
VCC = +2.85V to +3.9V, TA = -40°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN).) (See Figure 9.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
fSCL
(Note 11)
0
400
kHz
Clock Pulse-Width Low
tLOW
1.3
s
Clock Pulse-Width High
tHIGH
0.6
s
Bus-Free Time Between STOP and
START Condition
tBUF
1.3
s
Start Hold Time
tHD:STA
0.6
s
Start Setup Time
tSU:STA
0.6
s
Data in Hold Time
tHD:DAT
0
0.9
s
Data in Setup Time
tSU:DAT
100
ns
Rise Time of Both SDA and SCL
Signals
tR
(Note 12)
20 +
0.1CB
300
ns
Fall Time of Both SDA and SCL
Signals
tF
(Note 12)
20 +
0.1CB
300
ns
STOP Setup Time
tSU:STO
0.6
s
Capacitive Load for Each Bus Line
CB
(Note 12)
400
pF
EEPROM Write Time
tW
(Note 13)
20
ms
PON Triplexer Control and
Monitoring Circuit
_____________________________________________________________________
5
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.85V to +3.9V)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EEPROM Write Cycles
At +70°C
50,000
Note 1:
All voltages are referenced to ground. Current into IC is positive, out of the IC is negative.
Note 2:
Digital inputs are at rail. FETG is disconnected. SDA = SCL = VCC. DAC1 and M4DAC are not loaded.
Note 3:
See the
Safety Shutdown (FETG) Output section for details.
Note 4:
Eight ranges allow the full-scale range to change from 625mV to 2.5V.
Note 5:
This specification applies to the expected full-scale value for the selected range. See the Comp Ranging byte for available
full-scale ranges.
Note 6:
Eight ranges allow the BMD full-scale range to change from 312.5mV to 1.25V.
Note 7:
The output impedance of the DS1865 is proportional to its scale setting. For instance, if using the 1/2 scale, the output
impedance would be approximately 1.56k
Ω.
Note 8:
This specification applies to the expected full-scale value for the selected range. See the Mod Ranging byte for available
full-scale ranges.
Note 9:
See the
APC and Quick-Trip Shared Comparator Timing section for details.
Note 10: Assuming an appropriate initial step is programmed that would cause the power to exceed the APC set point within four
steps, the bias current will be 1% within the time specified by the binary search time. See the
Bias and MOD Output During
Power-Up section.
Note 11: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with the I2C stan-
dard mode.
Note 12: CB
total capacitance of one bus line in picofarads.
Note 13: EEPROM write begins after a STOP condition occurs.
Note 14: Guaranteed by design.
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