参数资料
型号: DS1873T+T&R
厂商: Maxim Integrated
文件页数: 13/86页
文件大小: 0K
描述: IC CTLR SFP+ ANLG LDD 28-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 激光二极管控制器
通道数: 1
电源电压: 2.85 V ~ 3.9 V
电流 - 电源: 2.5mA
工作温度: -40°C ~ 95°C
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 带卷 (TR)
安装类型: 表面贴装
其它名称: 90-1873T+TRL
SFP+ Controller with Analog LDD Interface
Table 1. Acronyms
ACRONYM
DEFINITION
BIAS and MOD Output Control
During Power-Up
On power-up, the DS1873 sets the MOD and BIAS
ADC
AGC
APC
APD
ATB
BM
DAC
LOS
LUT
NV
QT
TE
TIA
ROSA
SEE
SFF
SFF-8472
SFP
SFP+
TOSA
TXP
Analog-to-Digital Converter
Automatic Gain Control
Automatic Power Control
Avalanche Photodiode
Alarm Trap Bytes
Burst Mode
Digital-to-Analog Converter
Loss of Signal
Lookup Table
Nonvolatile
Quick Trip
Tracking Error
Transimpedance Amplifier
Receiver Optical Subassembly
Shadowed EEPROM
Small Form Factor
Document Defining Register Map of SFPs
and SFFs
Small Form Factor Pluggable
Enhanced SFP
Transmit Optical Subassembly
Transmit Power
V POA
V CC
DACs to 0. After a temperature conversion is complet-
ed and if the VCC LO alarm is enabled, an additional
V CC conversion above the customer-defined VCC LO
alarm level is required before the MOD DAC is updated
with the value determined by the temperature conver-
sion and the modulation LUT.
When the MOD DAC is set, the BIAS DAC is set to a
value equal to ISTEP (see Figure 1). The startup algo-
rithm checks if this bias current causes a feedback
voltage above the APC set point, and if not, it continues
increasing the BIAS DAC by ISTEP until the APC set-
point is exceeded. When the APC set point is exceed-
ed, the device begins a binary search to quickly reach
the bias current corresponding to the proper power
level. After the binary search is completed, the APC
integrator is enabled and single LSB steps are used to
tightly control the average power.
The TXP HI, TXP LO, HBAL, and BIAS MAX QT alarms
are masked until the binary search is completed.
However, the BIAS MAX alarm is monitored during this
time to prevent the BIAS DAC from exceeding IBIASMAX.
During the bias current initialization, the BIAS DAC is
not allowed to exceed IBIASMAX. If this occurs during
the ISTEP sequence, then the binary search routine is
t INIT
MOD DAC
t SEARCH
4x ISTEP
BIAS DAC
3x ISTEP
2x ISTEP
ISTEP
BINARY SEARCH
APC INTEGRATOR ON
BIAS SAMPLE
1
2
3
4
5
6
7
8
9
10
11
12
13
Figure 1. Power-Up Timing
______________________________________________________________________________________
13
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