参数资料
型号: DS1873T+T&R
厂商: Maxim Integrated
文件页数: 17/86页
文件大小: 0K
描述: IC CTLR SFP+ ANLG LDD 28-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 激光二极管控制器
通道数: 1
电源电压: 2.85 V ~ 3.9 V
电流 - 电源: 2.5mA
工作温度: -40°C ~ 95°C
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 带卷 (TR)
安装类型: 表面贴装
其它名称: 90-1873T+TRL
SFP+ Controller with Analog LDD Interface
Table 3. MON3 Hysteresis Threshold
MON3
TIMESLICE
Values
NUMBER OF
RIGHT-SHIFTS
FINE MODE
MAX (hex)
COARSE MODE
MIN* (hex)
PERFORM FINE-
MODE CONVERSION
DID PRIOR MON3
0
1
2
3
4
FFF8
7FFC
3FFE
1FFF
0FFF
F000
7800
3C00
1E00
0F00
TIMESLICE RESULT IN A
COARSE CONVERSION?
(LAST RSSIR = 1?)
Y
5
6
7
07FF
03FF
01FF
0780
03C0
01E0
N
N
WAS CURRENT FINE-
*This is the minimum reported coarse-mode conversion.
MODE CONVERSION
≥ 93.75% OF FS?
Table 4. MON3 Configuration Registers
DID CURRENT FINE-
MODE CONVERSION
REACH MAX?
Y
Y
REGISTER
GAIN
FINE MODE
98h –99h, Table 02h
COARSE MODE
9Ch –9Dh, Table 02h
PERFORM COARSE-
OFFSET
A8h –A9h, Table 02h ACh –ADh, Table 02h
N
MODE CONVERSION
RIGHT-SHIFT 0
8Fh, Table 02h
CNFGC
8Bh, Table 02h
LAST RSSIR = 0
REPORT FINE
CONVERSION RESULT
LAST RSSIR = 1
REPORT COARSE
CONVERSION RESULT
UPDATE
(RSSIR BIT)
MON3 VALUE
6Fh, Lower Memory
68h –69h, Lower Memory
timeslice begins with a fine mode analog-to-digital con-
version (using fine mode’s gain, offset, and right-shifting
settings). See the flowchart in Figure 6 for more details.
Then, depending on whether the last MON3 timeslice
resulted in a coarse-mode conversion and also depend-
END OF MON3
TIMESLICE
Figure 6. RSSI Flowchart
Additional information for each of the registers can be
found in the Register Descriptions section.
Dual-range operation is transparent to the end user.
The results of MON3 analog-to-digital conversions are
still stored/reported in the same memory locations
(68h–69h, Lower Memory) regardless of whether the
conversion was performed in fine mode or coarse
mode. The only way to tell which mode generated the
digital result is by reading the RSSIR bit.
When the DS1873 is powered up, analog-to-digital con-
versions begin in a round-robin fashion. Every MON3
ing on the value of the current fine conversion, decisions
are made whether to use the current fine-mode conver-
sion result or to make an additional conversion (within
the same MON3 timeslice), using coarse mode (using
coarse mode’s gain and offset settings and no right-
shifting) and reporting the coarse-mode result. The flow-
chart in Figure 6 also illustrates how hysteresis is
implemented. The fine-mode conversion is compared to
one of two thresholds. The actual threshold values are a
function of the number of right-shifts being used. With
the use of right-shifting, the fine mode full-scale is pro-
grammed to (1/2 n th) of the coarse mode full-scale. The
DS1873 now auto ranges to choose the range that gives
the best resolution for the measurement. Hysteresis is
applied to eliminate chatter when the input resides at
the boundary of the two ranges. See Figure 6 for details.
Table 3 shows the threshold values for each possible
number of right-shifts.
______________________________________________________________________________________
17
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