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参数资料
| 型号： | DS1963S |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | Memory IC:Other |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, MEDB2 |
| 封装： | MICROCAN-2 |
| 文件页数： | 34/37页 |
| 文件大小： | 349K |
| 代理商： | DS1963S |
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DS1963S
6 of 37
1-WIRE CRC GENERATOR Figure 4
R
X2
X1
X0
X8
X7
X6
X5
X4
X3
8TH
STAGE
7TH
STAGE
6TH
STAGE
5TH
STAGE
4TH
STAGE
3RD
STAGE
2ND
STAGE
1ST
STAGE
S
INPUT DATA
Polynomial = X8 + X5 + X4 + 1
MEMORY MAP
As shown in the block diagram, the DS1963S has four memory areas: data memory, secrets memory,
counter memory, and scratchpad. Each of these memory areas is organized in pages of 32 bytes. Figure 5
shows details. The scratchpad acts as a buffer when writing to data or secrets memory. Pages 0 to 15 have
unrestricted read/write access. They account for the 4096 bits of NV SRAM. Pages 16 and 17 contain the
eight 64-bit secrets to which the user only has write access. The secrets are readable only by the SHA
engine, which uses them to compute message authentication codes. Sixteen 32-bit write-cycle counters
count write-accesses to pages 8 to 15 as well as to the eight secrets. These counters are located in pages
19 and 20 and can be read without restriction. Page 21 contains a counter, which increments with every
start of the SHA engine. This counter provides the seed for generating pseudo-random numbers and
therefore is referred to as PRNG counter. Since the SHA engine requires about 20 times as much energy
as copying the entire scratchpad to a memory location the PRNG counter can be used as indicator for the
remaining energy reserves of the device. Page 18 is the physical location of the 32-byte scratchpad.
ADDRESS REGISTERS AND TRANSFER STATUS
The DS1963S employs three address registers: TA1, TA2 and E/S (Figure 6). Registers TA1 and TA2
must be loaded with the target address to which data will be written or from which data will read.
Register E/S is a read-only byte counter and transfer-status register, used to verify data integrity with
write commands. The lower 5 bits of the E/S register indicate the address of the last byte that has been
written to the scratchpad for subsequent copying into main memory. This address is called Ending Offset.
Bit 5 of the E/S register, called PF or “partial byte flag,” is a logic-1 if the number of data bits sent by the
master is not an integer multiple of 8. Bit 6 has no function; it always reads 0. Note that the lowest 5 bits
of the target address also determine the address within the scratchpad where intermediate storage of data
will begin. This address is called byte offset. If the target address (TA1) for a Write command is 3CH for
example, then the scratchpad will store incoming data beginning at byte offset 1CH and will be full after
only 4 bytes, resulting in an ending offset of 1FH. The ending offset together with the Partial Flag support
the master checking the data integrity after a Write command. The highest valued bit of the E/S register,
called AA or Authorization Accepted, acts as a flag to indicate that the data stored in the scratchpad has
already been copied to the target memory address. Writing data to the scratchpad clears this flag.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1963S+F5 | 制造商:Maxim Integrated Products 功能描述:SHA IBTN 8SOIC - Rail/Tube |
| DS1963S-F5 | 功能描述:iButton RoHS:否 存储类型:SRAM 存储容量:512 B 组织: 工作电源电压:3 V to 5.25 V 接口类型:1-Wire 最大工作温度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封装 / 箱体:F5 MicroCan 制造商:Maxim Integrated |
| DS1963S-F5+ | 功能描述:iButton SHA iButton RoHS:否 存储类型:SRAM 存储容量:512 B 组织: 工作电源电压:3 V to 5.25 V 接口类型:1-Wire 最大工作温度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封装 / 箱体:F5 MicroCan 制造商:Maxim Integrated |
| DS1965S-1-F3 | 功能描述:iButton RoHS:否 存储类型:SRAM 存储容量:512 B 组织: 工作电源电压:3 V to 5.25 V 接口类型:1-Wire 最大工作温度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封装 / 箱体:F5 MicroCan 制造商:Maxim Integrated |
| DS1965S-1-F5 | 功能描述:iButton RoHS:否 存储类型:SRAM 存储容量:512 B 组织: 工作电源电压:3 V to 5.25 V 接口类型:1-Wire 最大工作温度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封装 / 箱体:F5 MicroCan 制造商:Maxim Integrated |
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