参数资料
| 型号： | DS21448 |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 38/60页 |
| 文件大小： | 0K |
| 描述： | IC LIU QUAD E1/T1/J1 144-BGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 4/4 |
| 规程： | T1/E1/J1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-BGA |
| 供应商设备封装： | 144-TEPBGA（17x17） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页当前第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页
DS21448 3.3V T1/E1/J1 Quad Line Interface
43 of 60
8. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
The DS21448 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and
EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE (Table 8-A). The DS21448
contains the following items, which meet the requirements set by the IEEE 1149.1 Standard Test Access Port
(TAP) and Boundary Scan Architecture:
Test Access Port
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
The TAP has the necessary interface pins JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin descriptions in
Section 1 for details. Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE
1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
Figure 8-1. JTAG Block Diagram
8.1 JTAG TAP Controller State Machine
This section covers the operation of the TAP controller state machine. See Figure 8-2 for details on each of the
states described below. The TAP controller is a finite state machine that responds to the logic level at JTMS on the
rising edge of JTCLK (Table 8-B).
Test-Logic-Reset. Upon power-up, the TAP controller is in test-logic-reset state. The instruction register contains
the IDCODE instruction. All system logic of the device operates normally.
Run-Test-Idle. The run-test-idle is used between scan operations or during specific tests. The instruction register
and test registers remain idle.
Select-DR-Scan. All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the
controller into the capture-DR state and initiates a scan sequence. JTMS HIGH during a rising edge on JTCLK
moves the controller to the select-IR-scan state.
JTDI
JTMS
JTCLK
JTRST
JTDO
TEST ACCESS PORT
CONTROLLER
VDD
BOUNDRY SCAN
REGISTER
BYPASS
REGISTER
INSTRUCTION
REGISTER
IDENTIFICATION
REGISTER
MUX
SELECT
OUTPUT ENABLE
10k
10k
10k
相关PDF资料 |
PDF描述 |
|---|---|
| DS3151N+ | IC LIU DS3/E3/STS-1 144CSBGA |
| VI-24L-MX-F3 | CONVERTER MOD DC/DC 28V 75W |
| D38999/24JB5HN | CONN RCPT 5POS JAM NUT W/PINS |
| VI-24L-MX-F2 | CONVERTER MOD DC/DC 28V 75W |
| HI7191IB | IC ADC 24BIT PROGBL SER 20-SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS21448A1 | 功能描述:网络控制器与处理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21448DK | 功能描述:网络开发工具 DS21448 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
| DS21448G+ | 功能描述:网络控制器与处理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21448GN+ | 功能描述:网络控制器与处理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21448L | 功能描述:网络控制器与处理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
发布紧急采购，3分钟左右您将得到回复。