参数资料
| 型号： | DS21448 |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 4/60页 |
| 文件大小： | 0K |
| 描述： | IC LIU QUAD E1/T1/J1 144-BGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 4/4 |
| 规程： | T1/E1/J1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-BGA |
| 供应商设备封装： | 144-TEPBGA（17x17） |
| 包装： | 管件 |
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DS21448 3.3V T1/E1/J1 Quad Line Interface
12 of 60
PIN
I/O
FUNCTION
CES
I
Receive and Transmit Clock Select. Selects which RCLK edge to update RPOS and RNEG and
which TCLK edge to sample TPOS and TNEG. CES combines TCES and RCES.
0 = update RPOS/RNEG on rising edge of RCLK; sample TPOS/TNEG on falling edge of TCLK
1 = update RPOS/RNEG on falling edge of RCLK; sample TPOS/TNEG on rising edge of TCLK
TPD
I
Transmit Power-Down
0 = normal transmitter operation
1 = powers down the transmitter and tri-states TTIP and TRING pins
TX0/TX1
I
Transmit Data Source Select Bits 0 and 1. These inputs determine the source of the transmit
data (Table 4-B).
LOOP0/LOOP1
I
Loopback Select Bits 0 and 1. These inputs determine the active loopback mode (Table 4-A).
MM0/MM1
I
Monitor Mode Select Bits 0 and 1. These inputs determine if the receive equalizer is in a monitor
mode (Table 4-D).
RT1/RT0
I
Receive LIU Termination Select Bits 0 and 1. These inputs determine the receive termination
TEST
I
Tri-State Control. Set high to tri-state all outputs and I/O pins (including the parallel control port).
Set low for normal operation. Useful in board-level testing.
HRST
I
Hardware Reset. Bringing
HRST low resets the DS21448, setting all control bits to the all-zero
default state.
MCLK
I
Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This
clock is used internally for both clock/data recovery and for jitter attenuation. A T1 1.544MHz
clock source is optional (Note 1). See Table 4-F for details.
BIS0/BIS1
I
Bus Interface Select Bit 0 and 1. Used to select bus interface option (Table 2-A).
EGL1–EGL4
I
Receive Equalizer Gain-Limit Select. These bits control the sensitivity of the receive equalizers
PBEO1–PBEO4
O
PRBS Bit-Error Output. The receiver constantly searches for a 2
15 - 1 PRBS (ETS = 0) or a
QRSS PRBS (ETS = 1). The pattern is chosen automatically by the value of the ETS pin. It
remains high if it is out of synchronization with the PRBS pattern. It goes low when synchronized
to the PRBS pattern. Any errors in the received pattern after synchronization cause a positive-
going pulse (with same period as E1 or T1 clock) synchronous with RCLK.
RCL1–RCL4
O
Receive Carrier Loss. An output that toggles high during a receive carrier loss.
RTIP1–RTIP4
I
RRING1–RRING4
I
Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect through a
1:1 transformer to the line. See Section 7 for details.
BPCLK1–BPCLK4
O
Backplane Clock. A 16.384MHz clock output that is referenced to RCLK.
TTIP1–TTIP4
TRING1–TRING4
O
Transmit Tip and Ring. Analog line-driver outputs. These pins connect through a step-up
transformer to the line. See Section 7 for details.
RPOS1–RPOS4
O
Receive Positive Data. Updated on the rising edge (CES = 0) or the falling edge (CES = 1) of
RCLK with bipolar data out of the line interface. In NRZ mode (NRZE = 1), data is output on
RPOS, and a received error (BPV, CV, or EXZ) causes a positive-going pulse synchronous with
RCLK at RNEG.
RNEG1–RNEG4
O
Receive Negative Data. Updated on the rising edge (CES = 0) or the falling edge (CES = 1) of
RCLK with bipolar data out of the line interface. In NRZ mode (NRZE = 1), data is output on
RPOS, and a received error (BPV, CV, or EXZ) causes a positive-going pulse synchronous with
RCLK at RNEG.
RCLK1–RCLK4
O
Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK in absence of
signal at RTIP and RRING.
TPOS1–TPOS4
I
Transmit Positive Data. Sampled on the falling edge (CES = 0) or the rising edge (CES = 1) of
TCLK for data to be transmitted out onto the line.
TNEG1–TNEG4
I
Transmit Negative Data. Sampled on the falling edge (CES = 0) or the rising edge (CES = 1) of
TCLK for data to be transmitted out onto the line.
TCLK1–TCLK4
I
Transmit Clock. A 2.048MHz or 1.544MHz primary clock used to clock data through the transmit
side formatter. It can be sourced internally by MCLK or RCLK. See Common Control Register 1
and Figure 1-3.
JTRST
I
JTAG Reset
JTMS
I
JTAG Mode Select
JTCLK
I
JTAG Clock
JTDI
I
JTAG Data In
JTDO
O
JTAG Data Out
VSM
I
Voltage Supply Mode (LQFP only). VSM should be wired low for correct operation.
TVDD1–TVDD4
–
3.3V, ±5% Transmitter Positive Supply
VDD1–VDD4
—
3.3V, ±5% Positive Supply
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS21448A1 | 功能描述:网络控制器与处理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21448DK | 功能描述:网络开发工具 DS21448 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
| DS21448G+ | 功能描述:网络控制器与处理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21448GN+ | 功能描述:网络控制器与处理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21448L | 功能描述:网络控制器与处理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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