参数资料
型号: DS2156DK
厂商: Maxim Integrated Products
文件页数: 7/21页
文件大小: 0K
描述: KIT DESIGN FOR DS2156
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
主要目的: 电信,线路接口单元(LIU)
已用 IC / 零件: DS2156
DS2155DK/DS2156DK T1/E1/J1 Single-Chip Transceiver Design Kit Daughter Cards
SWITCH2: PIN TO 2.048MHz (Offset = 0X0012) INITIAL VALUE = 0x3
(MSB)
(LSB)
MCLK
TCLK
RSYSCLK
TSYSCLK
NAME
MCLK
TCLK
RSYSCLK
TSYSCLK
POSITION
SWITCH2.3
SWITCH2.2
SWITCH2.1
SWITCH2.0
FUNCTION
0 = Connect MCLK to the 2.048MHz clock
1 = Open Switch 2.4
0 = Connect TCLK to the 2.048MHz clock
1 = Open Switch 2.3
0 = Connect RSYSCLK to the 2.048MHz clock
1 = Open Switch 2.2
0 = Connect TSYSCLK to the 2.048MHz clock
1 = Open Switch 2.1
SWITCH3: PIN-TO-PIN CONNECT (Offset = 0X0013) INITIAL VALUE = 0xF
(MSB)
(LSB)
TSS_RS
TCL_RC
RSY_RC
TSY_RC
NAME
TSS_RS
TCL_RC
RSY_RC
TSY_RC
POSITION
SWITCH3.3
SWITCH3.2
SWITCH3.1
SWITCH3.0
FUNCTION
0 = Connect TSSYNC to RSYNC
1 = Open Switch 3.4
0 = Connect TCLK to RCLK
1 = Open Switch 3.3
0 = Connect RSYSCLK to RCLK
1 = Open Switch 3.2
0 = Connect TSYSCLK to RCLK
1 = Open Switch 3.1
SWITCH4: PIN-TO-PIN CONNECT (Offset = 0X0014) INITIAL VALUE = 0x3
(MSB)
(LSB)
UTCLK_2048 UT_CLK_2048 RSER_TSER RSYNC_TSYNC
NAME
URCLK_2048
UTCLK_2048
RSER_TSER
RSYNC_TSYNC
POSITION
SWITCH4.3
SWITCH4.2
SWITCH4.1
SWITCH4.0
FUNCTION
0 = Connect UR_CLK (TSSYNC) to 2.048MHz
1 = Open Switch 4.4
0 = Connect UT_CLK (TCHCLK) to 2.048MHz
1 = Open Switch 4.3
0 = Connect RER to TSER
1 = Open Switch 4.2
0 = Connect RSYNC to TSYNC
1 = Open Switch 4.1
7 of 21
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