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参数资料
| 型号： | DS21Q43-ATN |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 30/60页 |
| 文件大小： | 0K |
| 描述： | IC FRAMER E1 QUAD 5V 128-TQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 72 |
| 控制器类型： | E1 调帧器 |
| 接口： | 并行/串行 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 电流 - 电源： | 32mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-LQFP（14x20） |
| 包装： | 管件 |
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DS21Q43A
36 of 60
7.0 SIGNALING OPERATION
The Channel Associated Signaling (CAS) bits embedded in the E1 stream can be extracted from the
receive stream and inserted into the transmit stream by the DS21Q43A. Each of the 30 channels has four
signaling bits (A/B/C/D) associated with it. The numbers in parenthesis () are the channel associated with
a particular signaling bit. The channel numbers have been assigned as described in the ITU/CCITT
documents. For example, channel 1 is associated with timeslot 1 and channel 30 is associated with
timeslot 31. There is a set of 16 registers for the receive side (RS1 to RS16) and 16 registers on the
transmit side (TS1 to TS16). The signaling registers are detailed below.
RS1 TO RS16: RECEIVE SIGNALING REGISTERS (Address=30 to 3F Hex)
(MSB)
(LSB)
0
X
Y
X
RS1 (30)
A(1)
B(1)
C(1)
D(1)
A(16)
B(16)
C(16)
D(16)
RS2 (31)
A(2)
B(2)
C(2)
D(2)
A(17)
B(17)
C(17)
D(17)
RS3 (32)
A(3)
B(3)
C(3)
D(3)
A(18)
B(18)
C(18)
D(18)
RS4 (33)
A(4)
B(4)
C(4)
D(4)
A(19)
B(19)
C(19)
D(19)
RS5 (34)
A(5)
B(5)
C(5)
D(5)
A(20)
B(20)
C(20)
D(20)
RS6 (35)
A(6)
B(6)
C(6)
D(6)
A(21)
B(21)
C(21)
D(21)
RS7 (36)
A(7)
B(7)
C(7)
D(7)
A(22)
B(22)
C(22)
D(22)
RS8 (34)
A(8)
B(8)
C(8)
D(8)
A(23)
B(23)
C(23)
D(23)
RS9 (35)
A(9)
B(9)
C(9)
D(9)
A(24)
B(24)
C(24)
D(24)
RS10 (36)
A(10)
B(10)
C(10)
D(10)
A(25)
B(25)
C(25)
D(25)
RS11 (3A)
A(11)
B(11)
C(11)
D(11)
A(26)
B(26)
C(26)
D(26)
RS12 (3B)
A(12)
B(12)
C(12)
D(12)
A(27)
B(27)
C(27)
D(27)
RS13 (3C)
A(13)
B(13)
C(13)
D(13)
A(28)
B(28)
C(28)
D(28)
RS14 (3D)
A(14)
B(14)
C(14)
D(14)
A(29)
B(29)
C(29)
D(29)
RS15 (3E)
A(15)
B(15)
C(15)
D(15)
A(30)
B(30)
C(30)
D(30)
RS16 (3F)
SYMBOL
POSITION
NAME AND DESCRIPTION
X
RS1.0/1/3
Spare Bits.
Y
RS1.2
Remote Alarm Bit (integrated and reported in SR1.6).
A(1)
RS2.7
Signaling Bit A for Channel 1.
D(30)
RS16.0
Signaling Bit D for Channel 30.
Each Receive Signaling Register (RS1 to RS16) reports the incoming signaling bits from two timeslots.
The bits in the Receive Signaling Registers are updated on multiframe boundaries so the user can utilize
the Receive Multiframe Interrupt in the Receive Status Register 2 (SR2.7) to know when to retrieve the
signaling bits. The user has a full 2 ms to retrieve the signaling bits before the data is lost. The RS
registers are updated under all conditions. Their validity should be qualified by checking for
synchronization at the CAS level. In CCS signaling mode, RS1 to RS16 can also be used to extract
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| DS21Q44T | 功能描述:网络控制器与处理器 IC Enhanced Quad E1 Framer RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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