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参数资料
| 型号： | DS2431P |
| 元件分类： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 该CAT24FC02是一个2 KB的EEPROM的国内256个8位每字举办的串行CMOS |
| 文件页数： | 13/23页 |
| 文件大小： | 170K |
| 代理商： | DS2431P |
DS2431: 1024-Bit, 1-Wire EEPROM
13 of 23
READ SCRATCHPAD COMMAND [AAh]
The Read Scratchpad command allows verifying the target address and the integrity of the scratchpad data. After
issuing the command code, the master begins reading. The first two bytes are the target address. The next byte is
the ending offset/data status byte (E/S) followed by the scratchpad data, which may be different from what the
master originally sent. This is of particular importance if the target address is within the register page or a page in
either Write Protection or EPROM modes. See the Write Scratchpad description for details. The master should
read through the scratchpad (E2:E0 – T2:T0 + 1 bytes), after which it will receive the inverted CRC, based on data
as it was sent by the DS2431. If the master continues reading after the CRC, all data will be logic 1s.
COPY SCRATCHPAD [55h]
The Copy Scratchpad command is used to copy data from the scratchpad to writable memory sections. After
issuing the Copy Scratchpad command, the master must provide a 3-byte authorization pattern, which should have
been obtained by an immediately preceding Read Scratchpad command. This 3-byte pattern must exactly match
the data contained in the three address registers (TA1, TA2, E/S, in that order). If the pattern matches, the target
address is valid, the PF flag is not set, and the target memory is not copy-protected, the AA (Authorization
Accepted) flag is set and the copy begins. All eight bytes of scratchpad contents are copied to the target memory
location. The device’s internal data transfer takes 13ms maximum during which the voltage on the 1-Wire bus must
not fall below 2.8V. A pattern of alternating 0s and 1s are transmitted after the data has been copied until the
master issues a reset pulse. If the PF flag is set or the target memory is copy-protected, the copy will not begin and
the AA flag will not be set.
READ MEMORY [F0h]
The Read Memory command is the general function to read data from the DS2431. After issuing the command, the
master must provide the 2-byte target address. After these two bytes, the master reads data beginning from the
target address and may continue until address 008Fh. If the master continues reading, the result will be logic 1s.
The device's internal TA1, TA2, E/S, and scratchpad contents are not affected by a Read Memory command.
1-Wire BUS SYSTEM
The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the DS2431 is a
slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into
three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). The
1-Wire protocol defines bus transactions in terms of the bus state during specific time slots, which are initiated on
the falling edge of sync pulses from the bus master.
HARDWARE CONFIGURATION
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at
the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open-drain or tri-state
outputs. The 1-Wire port of the DS2431 is open drain with an internal circuit equivalent to that shown in Figure 8.
A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The DS2431 supports both a Standard and
Overdrive communication speed of 15.4kbps (max) and 111kbps (max), respectively. Note that legacy 1-Wire
products support a standard communication speed of 16.3kbps and Overdrive of 142kbps. The slightly reduced
rates for the DS2431 are a result of additional recovery times, which in turn were driven by a 1-Wire physical
interface enhancement to improve noise immunity. The value of the pullup resistor primarily depends on the
network size and load conditions. The DS2431 requires a pullup resistor of 2.2k
(max) at any speed.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be
left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 16μs
(Overdrive speed) or more than 120μs (standard speed), one or more devices on the bus may be reset.
相关PDF资料 |
PDF描述 |
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| DS2431X | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| DS2441 | 1-Cell Li-Ion Battery Manager |
| DS2450 | 1-Wire Quad A/D Converter |
| DS2450S | 1-Wire Quad A/D Converter |
| DS2480 | Serial 1.Wire Line Driver |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS2431P R | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:1024-Bit, 1-Wire EEPROM |
| DS2431P T | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:1024-Bit, 1-Wire EEPROM |
| DS2431P/R | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:1024-Bit 1-Wire EEPROM |
| DS2431P/T | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:1024-Bit 1-Wire EEPROM |
| DS2431P/T&R | 功能描述:电可擦除可编程只读存储器 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
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