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参数资料
| 型号： | DS2438Z+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 19/29页 |
| 文件大小： | 0K |
| 描述： | IC MONITOR SMART BATTERY 8-SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 功能： | 燃料，电量检测计/监控器 |
| 电池化学： | 智能电池 |
| 电源电压： | 2.4 V ~ 10 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 带卷 (TR) |
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DS2438
3. The bus master reads a bit from the 1-Wire bus. Each device will respond by placing the value of the
first bit of their respective ROM data onto the 1-Wire bus. ROM1 and ROM4 will place a 0 onto the
1-Wire bus, i.e., pull it low. ROM2 and ROM3 will place a 1 onto the 1-Wire bus by allowing the line
to stay high. The result is the logical AND of all devices on the line; therefore the bus master sees a 0.
The bus master reads another bit. Since the Search ROM data command is being executed, all of the
devices on the 1-Wire bus respond to this second read by placing the complement of the first bit of
their respective ROM data onto the 1-Wire bus. ROM1 and ROM4 will place a 1 onto the 1-wire,
allowing the line to stay high. ROM2 and ROM3 will place a 0 onto the 1-wire, thus it will be pulled
low. The bus master again observes a 0 for the complement of the first ROM data bit. The bus master
has determined that there are some devices on the 1-Wire bus that have a 0 in the first position and
others that have a 1.
The data obtained from the two reads of the three-step routine have the following interpretations:
00 - There are still devices attached which have conflicting bits in this position.
01 - All devices still coupled have a 0 bit in this bit position.
10 - All devices still coupled have a 1 bit in this bit position.
11 - There are no devices attached to the 1-Wire bus.
4. The bus master writes a 0. This deselects ROM2 and ROM3 for the remainder of this search pass,
leaving only ROM1 and ROM4 connected to the 1-Wire bus.
5. The bus master performs two more reads and receives a 0 bit followed by a 1 bit. This indicates that
all devices still coupled to the bus have 0s as their second ROM data bit.
6. The bus master then writes a 0 to keep both ROM1 and ROM4 coupled.
7. The bus master executes two reads and receives two 0 bits. This indicates that both 1 bits and 0 bits
exist as the 3rd bit of the ROM data of the attached devices.
8. The bus master writes a 0 bit. This deselects ROM1, leaving ROM4 as the only device still connected.
9. The bus master reads the remainder of the ROM bits for ROM4 and continues to access the part if
desired. This completes the first pass and uniquely identifies one part on the 1-Wire bus.
10. The bus master starts a new ROM search sequence by repeating steps 1 through 7.
11. The bus master writes a 1 bit. This decouples ROM4, leaving only ROM1 still coupled.
12. The bus master reads the remainder of the ROM bits for ROM1 and communicates to the underlying
logic if desired. This completes the second ROM search pass, in which another of the ROMs was
found.
13. The bus master starts a new ROM search by repeating steps 1 through 3.
14. The bus master writes a 1 bit. This deselects ROM1 and ROM4 for the remainder of this search pass,
leaving only ROM2 and ROM3 coupled to the system.
15. The bus master executes two read time slots and receives two 0s.
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