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参数资料
| 型号： | DS2450S+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 11/25页 |
| 文件大小： | 0K |
| 描述： | IC CONVERTER A/D QUAD 1-W 8-SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 产品变化通告： | Product Discontinuation 27/Jul/12 |
| 标准包装： | 2,000 |
| 位数： | 16 |
| 采样率（每秒）： | 1k |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 2.5mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.209"，5.30mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 4 个单端，单极 |
DS2450
19 of 24
INITIALIZATION PROCEDURE “RESET AND PRESENCE PLUSES” Figure 10
*IN ORDER NOT TO MASK INTERRUPT SIGNALING BY OTHER DEVICES ON THE 1-WIRE BUS, tRSTL + tR
SHOULD ALWAYS BE LESS THAN 960 μs
**INCLUDES RECOVERY TIME
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated in Figure 11. All time slots are initiated by the
master driving the data line low. The falling edge of the data line synchronizes the DS2450 to the master
by triggering a delay circuit in the DS2450. During write time slots, the delay circuit determines when
the DS2450 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay
circuit determines how long the DS2450 will hold the data line low overriding the 1 generated by the
master. If the data bit is a “1”, the device will leave the read data time slot unchanged.
READ/WRITE TIME DIAGRAM
Figure 11
Write-one Time Slot
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS245CEDX | 制造商:CUTLER HAMMER/EATON 功能描述: 制造商:Eaton Corporation 功能描述: 制造商:Eaton Corporation 功能描述:RWD |
| DS246 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog IC |
| DS2460 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:SHA-1 Coprocessor with EEPROM |
| DS2460+ | 制造商:Maxim Integrated Products 功能描述: |
| DS2460S | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:SHA-1 Coprocessor with EEPROM |
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