参数资料
型号: DS2450S+T&R
厂商: Maxim Integrated Products
文件页数: 19/25页
文件大小: 0K
描述: IC CONVERTER A/D QUAD 1-W 8-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
产品变化通告: Product Discontinuation 27/Jul/12
标准包装: 2,000
位数: 16
采样率(每秒): 1k
数据接口: 串行
转换器数目: 1
功率耗散(最大): 2.5mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.209",5.30mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
输入数目和类型: 4 个单端,单极
DS2450
3 of 24
HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2
The DS2450 uses the standard Dallas Semiconductor 1-Wire protocol for data transfers. Communication
to and from the DS2450 requires a single bi-directional line that is typically a port pin of a
microcontroller. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The 1-Wire bus
master must first provide one of the seven ROM Function Commands, 1) Read ROM, 2) Match ROM, 3)
Search ROM, 4) Conditional Search ROM, 5) Skip ROM, 6) Overdrive-Skip ROM or 7) Overdrive-
Match ROM. Upon completion of an overdrive ROM command byte executed at standard speed, the
device will enter Overdrive mode where all subsequent communication occurs at a higher speed. The
protocol required for these ROM function commands is described in Figure 9. After a ROM function
command is successfully executed, the memory and control functions become accessible and the master
may provide any one of the available commands. The protocol for these commands is described in Figure
6. All data is read and written least significant bit first.
64-BIT LASERED ROM
Each DS2450 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family
code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (See
Figure 3.) The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and
XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the
Dallas 1-Wire Cyclic Redundancy Check is available in the Book of DS19xx iButtonTM Standards. The
shift register acting as the CRC accumulator is initialized to zero. Then starting with the least significant
bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered,
then the serial number is entered. After the 48th bit of the serial number has been entered, the shift
register contains the CRC value. Shifting in the eight bits of CRC should return the shift register to all
zeros.
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