参数资料
型号: DS24B33S+T&R
厂商: Maxim Integrated Products
文件页数: 12/23页
文件大小: 0K
描述: IC EEPROM 4KBIT 8SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,000
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 4K (256 x 16)
接口: 1 线
电源电压: 2.8 V ~ 5.25 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.209",5.30mm 宽)
供应商设备封装: 8-SO
包装: 带卷 (TR)
DS24B33
1-Wire 4Kb EEPROM
Read Memory [F0h]
The Read Memory command is the general function to
read from the DS24B33. After issuing the command,
the master must provide a 2-byte target address, which
should be in the range of 0000h to 01FFh. If the target
address is higher than 01FFh, the DS24B33 changes
the upper 7 address bits to 0. After the address is
transmitted, the master reads data starting at the (modi-
fied) target address and can continue until address
01FFh. If the master continues reading, the result is
FFh. The Read Memory command can be ended at any
point by issuing a reset pulse. Note that the (modified)
target address provided with the Read Memory com-
mand overwrites the target address that was specified
with a previously issued Write Scratchpad command.
The Read Memory command overwrites the scratchpad
with data from the target memory page. When reading
the last byte of a memory page, the scratchpad is
loaded with data from the next memory page. This
could cause unexpected data to be loaded into the
scratchpad.
V PUP
BUS MASTER
R PUP
1-Wire Bus System
The 1-Wire bus is a system that has a single bus master
and one or more slaves. In all instances the DS24B33 is
a slave device. The bus master is typically a microcon-
troller. The discussion of this bus system is broken
down into three topics: hardware configuration, trans-
action sequence, and 1-Wire signaling (signal types
and timing). The 1-Wire protocol defines bus transac-
tions in terms of the bus state during specific time slots,
which are initiated on the falling edge of sync pulses
from the bus master.
Hardware Configuration
The 1-Wire bus has only a single line by definition; it is
important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device
attached to the 1-Wire bus must have open-drain or
three-state outputs. The 1-Wire port of the DS24B33 is
open drain with an internal circuit equivalent to that
shown in Figure 8.
DS24B33 1-Wire PORT
Rx
DATA
Rx
Tx
Rx = RECEIVE
I L
Tx
Tx = TRANSMIT
Figure 8. Hardware Configuration
12
OPEN-DRAIN
PORT PIN
100 ? MOSFET
Maxim Integrated
相关PDF资料
PDF描述
DS24B33Q+T&R IC EEPROM 4KBIT 6TDFN-EP
DS24B33+T&R IC EEPROM 4KBIT TO92-3
395-026-521-802 CARD EDGE 26POS DL .100X.200 BLK
395-026-521-801 CARD EDGE 26POS DL .100X.200 BLK
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