参数资料
| 型号： | DS24B33S+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 13/23页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 4KBIT 8SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,000 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 4K (256 x 16) |
| 接口： | 1 线 |
| 电源电压： | 2.8 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.209"，5.30mm 宽） |
| 供应商设备封装： | 8-SO |
| 包装： | 带卷 (TR) |
DS24B33
1-Wire 4Kb EEPROM
A multidrop bus consists of a 1-Wire bus with multiple
slaves attached. The DS24B33 supports both a stan-
dard and overdrive communication speed of 15.4kbps
(maximum) and 125kbps (maximum), respectively, over
the full pullup voltage range. For pullup voltages of
+4.75V and higher, the DS24B33 also supports the
legacy communication speed of 16.3kbps and over-
drive speed of 142kbps. The slightly reduced rates for
the DS24B33 are a result of additional recovery times,
which in turn were driven by a 1-Wire physical interface
enhancement to improve noise immunity. The value of
the pullup resistor primarily depends on the network
size and load conditions. The DS24B33 requires a
pullup resistor of 2.2k ? (maximum) at any speed.
The idle state for the 1-Wire bus is high. If for any rea-
son a transaction must be suspended, the bus must be
left in the idle state if the transaction is to resume. If this
does not occur and the bus is left low for more than
16μs (overdrive speed) or more than 120μs (standard
speed), one or more devices on the bus may be reset.
Transaction Sequence
The protocol for accessing the DS24B33 through the
1-Wire port is as follows:
? Initialization
? ROM Function Commands
? Memory Function Commands
Read ROM [33h]
This command allows the bus master to read the
DS24B33’s 8-bit family code, unique 48-bit serial num-
ber, and 8-bit CRC. This command can only be used if
there is a single slave on the bus. If more than one
slave is present on the bus, a data collision occurs
when all slaves try to transmit at the same time (open
drain produces a wired-AND result). The resultant family
code and 48-bit serial number results in a mismatch of
the CRC.
Match ROM [55h]
The Match ROM command, followed by a 64-bit ROM
sequence, allows the bus master to address a specific
DS24B33 on a multidrop bus. Only the DS24B33 that
exactly matches the 64-bit ROM sequence responds to
the memory function command that follows. All other
slaves wait for a reset pulse. This command can be
used with a single device or multiple devices on the
bus.
Search ROM [F0h]
When a system is initially brought up, the bus master
might not know the number of devices on the 1-Wire
bus or their registration numbers. By taking advantage
of the bus’s wired-AND property, the master can use a
process of elimination to identify the registration num-
bers of all slave devices. For each bit of the registration
number, starting with the LSB, the bus master issues a
? Transaction/Data
Initialization
triplet of time slots. On the first slot, each slave device
participating in the search outputs the true value of its
registration number bit. On the second slot, each slave
All transactions on the 1-Wire bus begin with an initial-
ization sequence. The initialization sequence consists
of a reset pulse transmitted by the bus master followed
by presence pulse(s) transmitted by the slave(s). The
presence pulse lets the bus master know that the
DS24B33 is on the bus and is ready to operate. For
more details, see the 1-Wire Signaling section.
1-Wire ROM Function Commands
Once the bus master has detected a presence, it can
issue one of the seven ROM function commands that
the DS24B33 supports. All ROM function commands are
8 bits long. See Figure 9 for a list of these commands.
Maxim Integrated
device participating in the search outputs the comple-
mented value of its registration number bit. On the third
slot, the master writes the true value of the bit to be
selected. All slave devices that do not match the bit
written by the master stop participating in the search. If
both of the read bits are zero, the master knows that
slave devices exist with both states of the bit. By choos-
ing which state to write, the bus master branches in the
ROM code tree. After one complete pass, the bus mas-
ter knows the registration number of a single device.
Additional passes identify the registration numbers of
the remaining devices. Refer to Application Note 187:
1-Wire Search Algorithm for a detailed discussion and
an example.
13
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