参数资料
| 型号： | DS24B33S+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 7/23页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 4KBIT 8SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,000 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 4K (256 x 16) |
| 接口： | 1 线 |
| 电源电压： | 2.8 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.209"，5.30mm 宽） |
| 供应商设备封装： | 8-SO |
| 包装： | 带卷 (TR) |
DS24B33
1-Wire 4Kb EEPROM
The shift register bits are initialized to 0. Then, starting
with the LSB of the family code, one bit at a time is
shifted in. After the 8th bit of the family code has been
entered, the serial number is entered. After the last bit
of the serial number has been entered, the shift register
contains the CRC value. Shifting in the 8 bits of the
CRC returns the shift register to all 0s.
Memory
The DS24B33 EEPROM array (Figure 5) consists of 16
pages of 32 bytes each, starting at address 0000h and
ending at address 01FFh. In addition to the EEPROM,
the device has a 32-byte volatile scratchpad. Writes to
the EEPROM array are a two-step process. First, data
is written to the scratchpad and then copied into the
main array. The user can verify the data in the scratch-
pad prior to copying.
POLYNOMIAL = X 8 + X 5 + X 4 + 1
1ST
STAGE
2ND
STAGE
3RD
STAGE
4TH
STAGE
5TH
STAGE
6TH
STAGE
7TH
STAGE
8TH
STAGE
X 0
X 1
X 2
X 3
X 4
X 5
X 6
X 7
X 8
INPUT DATA
Figure 4. 1-Wire CRC Generator
32-BYTE INTERMEDIATE STORAGE SCRATCHPAD
ADDRESS
0000h to 001Fh
0020h to 003Fh
0040h to 01DFh
01E0h to 01FFh
Figure 5. Memory Map
Maxim Integrated
32-BYTE FINAL STORAGE EEPROM
32-BYTE FINAL STORAGE EEPROM
FINAL STORAGE EEPROM
32-BYTE FINAL STORAGE EPPROM
PAGE 0
PAGE 1
PAGES 2 to 14
PAGE 15
7
相关PDF资料 |
PDF描述 |
|---|---|
| DS24B33Q+T&R | IC EEPROM 4KBIT 6TDFN-EP |
| DS24B33+T&R | IC EEPROM 4KBIT TO92-3 |
| 395-026-521-802 | CARD EDGE 26POS DL .100X.200 BLK |
| 395-026-521-801 | CARD EDGE 26POS DL .100X.200 BLK |
| 395-026-521-204 | CARD EDGE 26POS DL .100X.200 BLK |
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