参数资料
| 型号： | DS2505P+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 14/24页 |
| 文件大小： | 0K |
| 描述： | IC OTP 16KBIT 6TSOC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 4,000 |
| 格式 - 存储器： | EPROMs |
| 存储器类型： | EPROM OTP |
| 存储容量： | 16K（16K x 1） |
| 接口： | 1 线 串行 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 6-LSOJ |
| 供应商设备封装： | 6-TSOC |
| 包装： | 带卷 (TR) |
DS2505
responds with the data from the selected EPROM Status address sent least significant bit first. This byte
contains the logical AND of all bytes written to this EPROM Status Byte address. If the EPROM Status
Byte contains 1s in bit positions where the byte issued by the master contained 0s, a Reset Pulse should
be issued and the current byte address should be programmed again. If the DS2505 EPROM Status byte
contains 0s in the same bit positions as the data byte, the programming was successful and the DS2505
will automatically increment its address counter to select the next byte in the EPROM Status data field.
The new 2-byte address will also be loaded into the 16-bit CRC generator as a starting value. The bus
master will issue the next byte of data using eight write time slots.
As the DS2505 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator
that has been preloaded with the current address and the result is a 16-bit CRC of the new data byte and
the new address. After supplying the data byte, the bus master will read this 16-bit CRC from the
DS2505 with 16 read time slots to confirm that the address incremented properly and the data byte was
received correctly. If the CRC is incorrect, a reset pulse must be issued and the Write Status command
sequence must be restarted. If the CRC is correct, the bus master will issue a programming pulse and the
selected byte in memory will be programmed.
Note that the initial pass through the Write Status flow chart will generate a 16-bit CRC value that is the
result of shifting the command byte into the CRC generator, followed by the 2 address bytes, and finally
the data byte. Subsequent passes through the Write Status flow chart due to the DS2505 automatically
incrementing its address counter will generate a 16-bit CRC that is the result of loading (not shifting) the
new (incremented) address into the CRC generator and then shifting in the new data byte.
For both of these cases, the decision to continue (to apply a program pulse to the DS2505) is made
entirely by the bus master, since the DS2505 will not be able to determine if the 16-bit CRC calculated by
the bus master agrees with the 16-bit CRC calculated by the DS2505. If an incorrect CRC is ignored and
a program pulse is applied by the bus master, incorrect programming could occur within the DS2505.
Also note that the DS2505 will always increment its internal address counter after the receipt of the eight
read time slots used to confirm the programming of the selected EPROM byte. The decision to continue
is again made entirely by the bus master; therefore if the EPROM data byte does not match the supplied
data byte but the master continues with the Write Status command, incorrect programming could occur
within the DS2505. The Write Status command sequence can be ended at any point by issuing a Reset
Pulse.
To save time when writing more than 1 consecutive byte of the DS2505’s status memory it is possible to
omit reading the 16-bit CRC which allows verification of data and address before the data is copied to the
EPROM memory. This saves 16 time slots or 976 μs for every byte to be programmed. This speed-
programming mode is accessed with the command code F5H instead of 55H. It follows basically the
same flow chart as the Write Status command, but skips sending the CRC immediately preceding the
program pulse. This command should only be used if the electrical contact between bus master and the
DS2505 is firm since a poor contact may result in corrupted data inside the EPROM status memory.
1-WIRE BUS SYSTEM
The 1-Wire bus is a system which has a single bus master and one or more slaves. In all instances, the
DS2505 is a slave device. The bus master is typically a microcontroller. The discussion of this bus
system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire
signaling (signal type and timing). A 1-Wire protocol defines bus transactions in terms of the bus state
during specified time slots that are initiated on the falling edge of sync pulses from the bus master. For a
more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards.
14 of 24
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS2505P-UNW | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:UniqueWare Add-Only Memory |
| DS2505P-UNW-1154 | 制造商:Maxim Integrated Products 功能描述: |
| DS2505P-UNW-PPPP | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:UniqueWare Add-Only Memory |
| DS2505T | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:16-kbit Add-Only Memory |
| DS2505TR | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:16-kbit Add-Only Memory |
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