参数资料
型号: DS26303DK
厂商: Maxim Integrated Products
文件页数: 8/43页
文件大小: 0K
描述: KIT DESIGN FOR DS26303
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
主要目的: 电信,线路接口单元(LIU)
已用 IC / 零件: DS26303
已供物品: 板,线缆,电源
DS26303 Design Kit
Figure 1. DS26303DK JTAG Chain
JTMS
JTCLK
SW4
JTAG
(U2)
(U19)
(U5)
(U6)
(U7)
JTDI
JTDO
ON-BOARD
μ C
FLASH MEM
FOR FPGA
GEN
FPGA
DS26303
FLASH MEM
FOR SPI
ONCE
SW4
JTMS
JTCLK
(U2)
JTDI
JTDO
ON-BOARD
μ C
Address/Data Bus Connector
The DS26303DK has a connector (J1) to monitor all local bus activity for the design kit. All the signals can be
captured with a high-impedance probe and displayed on an oscilloscope or logic analyzer. Note: If the FPGA
switch (SW5) is in the “OFF” position, the on-board microcontroller will no longer drive any data onto the local bus.
Therefore, the user can now connect the local bus of the DS26303 into another system without making any
modifications to the hardware. See Table 2 for specific pin information for connector J1.
Table 2. Address/Data Connector Pinout
PIN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
NAME
A8
A7
A6
A5
A4
A3
A2
A1
A0
MUX
CSFPGA
CSBERT
CSLIU
ALELIU
RD
WR
MODESEL
FUNCTION
Local Address Bit 8
Local Address Bit 7
Local Address Bit 6
Local Address Bit 5
Local Address Bit 4
Local Address Bit 3
Local Address Bit 2
Local Address Bit 1
Local Address Bit 0
Mux
Chip Select FPGA
Chip Select DS2174
Chip Select DS26303
Address Latch Enable
Read Signal
Write Signal
Mode Select
Not Used
PIN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34, 36
37–40
NAME
D0
D1
D2
D3
D4
D5
D6
D7
CLKE
RDY
OE
MOTEL
INT
FPGAEN
UIN1
UIN2
3.3V
GND
FUNCTION
Local Data Bit 0
Local Data Bit 1
Local Data Bit 2
Local Data Bit 3
Local Data Bit 4
Local Data Bit 5
Local Data Bit 6
Local Data Bit 7
SPI Clock Edge Select
Ready Handshake from LIU
Output Enable LIU
Motorola/Intel Select
Interrupt for DS26303
FPGA Enable Pin
User Input 1
User Input 2
Board 3.3V
Ground
8 of 43
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