参数资料
型号: DS26324GNA2+
厂商: Maxim Integrated Products
文件页数: 87/120页
文件大小: 0K
描述: IC INTERFACE LINE 16CH 256-CSBGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 40
类型: 线路接口装置(LIU)
驱动器/接收器数: 16/16
规程: LIN
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 256-LBGA,CSBGA
供应商设备封装: 256-CSBGA(17x17)
包装: 托盘
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
69 of 120
Register Name:
MC
Register Description:
Master Clock Select
Register Address:
06h
Bit #
7
6
5
4
3
2
1
0
Name
PCLKI1
PCLKI0
TECLKE
CLKAE
MPS1
MPS0
FREQS
PLLE
Default
0
Bits 7 and 6: PLL Clock Input [1:0] (PCLKI[1:0]). These bits select the input into to the PLL.
00: MCLK is used.
01: RCLK1 to 8 is used based on the selection in register CCR.
10: RCLK9 to 16 is used based on the selection in register CCR.
11: Reserved.
Bit 5: T1/E1 Clock Enable (TECLKE). When this bit is set the TECLK output is enabled. If not set TECLK will be
disabled and the TECLK output is a LOS output. TECLK requires PLLE to be set for correct functionality.
Bit 4: Clock A Enable (CLKAE). When this bit is set the CLKA output is enabled. If not set CLKA will be disabled
and the CLKA output is a LOS output. CLKA requires PLLE to be set for correct functionality.
Bits 3 and 2: Master Period Select [1:0] (MPS[1:0]). These bits MPS[1:0] selects the external MCLK frequency
for the DS26324. See Table 6-15 for details. This register when written to will also controller functionality of
Channels 9 to 16.
Bit 1: Frequency Select (FREQS). In conjunction with MPS[1:0] selects the external MCLK frequency for the
DS26324. If this bit is set the external Master clock can be 1.544MHz or multiple thereof. If not set the external
master clock can be 2.048MHz or multiple thereof. See Table 6-15 for details. This register when written to will also
controller functionality of Channels 9 to 16.
Bit 0: Phase Lock Loop Enable (PLLE). When this bit is set the phase lock loop is enabled. If not set MCLK will
be the applied input clock.
Table 6-15. DS26324 MCLK Selections
PLLE
MPS1, MPS0
MCLK,
MHz ±50ppm
FREQS
MODE
0
xx
1.544
x
T1
0
xx
2.048
x
E1
1
00
1.544
1
T1/J1 or E1
1
01
3.088
1
T1/J1 or E1
1
10
6.176
1
T1/J1 or E1
1
11
12.352
1
T1/J1 or E1
1
00
2.048
0
T1/J1 or E1
1
01
4.096
0
T1/J1 or E1
1
10
8.192
0
T1/J1 or E1
1
11
16.384
0
T1/J1 or E1
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