参数资料
型号: DS26503L
英文描述: T1/E1/J1 BITS Element
中文描述: T1/E1/J1收发BITS的元素
文件页数: 28/123页
文件大小: 995K
代理商: DS26503L
DS26503 T1/E1/J1 BITS Element
28 of 123
6.5 Transmitter Operating Modes
Table 6-6.Transmit Path Operating Mode
TMODE3
PIN 62
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Note 1:
TMODE2
PIN 48
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
TMODE1
PIN 49
0
0
1
1
0
0
0
1
1
1
0
0
1
1
0
0
1
1
TMODE0
PIN 14
0
1
0
1
0
0
1
0
0
1
0
1
0
1
0
1
0
1
TRANSMIT PATH OPERATING MODE
T1 D4
T1 ESF
J1 D4
J1 ESF
E1 FAS
E1 FAS + CAS
(Note 1)
Reserved
E1 CRC4
E1 CRC4 + CAS
(Note 1)
Reserved
E1 G.703 2048kHz Synchronization Interface
Reserved
Reserved
6312kHz Synchronization Interface
(Note 2)
Reserved
Reserved
Reserved
Reserved
The DS26503 does not have an internal source for CAS signaling and multiframe alignment generation. CAS
signaling, and the multiframe alignment word, must be embedded in the transmit data (in the TS16 position) present
on the TSER pin and frame aligned to sync signal on the TS pin.
In addition to setting the TMODE bits to 6312kHz Synchronization Interface mode, the Transmit PLL must also be
configured to transmit a 6312kHz signal through the Transmit PLL Control Register (TPCR.6 and TPCR.7).
Note 2:
6.6 MCLK Pre-Scaler
Table 6-7. MCLK Pre-Scaler for T1 Mode
MPS1
PIN 16
0
0
1
1
0
0
1
1
MPS0
PIN 15
0
1
0
1
0
1
0
1
JACKS
PIN 46
0
0
0
0
1
1
1
1
MCLK
(MHz)
1.544
3.088
6.176
12.352
2.048
4.096
8.192
16.384
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