参数资料
型号: DS26503L
英文描述: T1/E1/J1 BITS Element
中文描述: T1/E1/J1收发BITS的元素
文件页数: 47/123页
文件大小: 995K
代理商: DS26503L
DS26503 T1/E1/J1 BITS Element
47 of 123
Table 9-1. E1 Sync/Resync Criteria
FRAME OR
MULTIFRAME
LEVEL
FAS
SYNC CRITERIA
RESYNC CRITERIA
ITU SPEC.
FAS present in frame N and
N + 2, and FAS not present in
frame N + 1
Three consecutive incorrect FAS
received
Alternate: (E1RCR.2 = 1) The above
criteria is met or three consecutive
incorrect bit 2 of non-FAS received
915 or more CRC4 code words out of
1000 received in error
Two consecutive MF alignment
words received in error
G.706
4.1.1
4.1.2
CRC4
Two valid MF alignment
words found within 8ms
Valid MF alignment word
found and previous time slot
16 contains code other than
all zeros
G.706
4.2 and 4.3.2
G.732 5.2
CAS
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
Bit 0/Unused, must be set = 0 for proper operation.
Bit 1/Transmit HDB3 Enable (THDB3).
0 = HDB3 disabled
1 = HDB3 enabled
Bit 2/Unused, must be set = 0 for proper operation.
Bit 3/Unused, must be set = 0 for proper operation.
Bit 4/ Transmit International Bit Select (TSiS)
0 = sample Si bits at TSER pin
1 = source Si bits from TAF and TNAF registers (in this mode, E1TCR1.7 must be set to 0)
Bit 5/Unused, must be set = 0 for proper operation.
Bit 6/Unused, must be set = 0 for proper operation.
Bit 7/ Transmit Time Slot 0 Pass-Through (TFPT)
0 = FAS bits/Sa bits/remote alarm sourced internally from the TAF and TNAF registers
1 = FAS bits/Sa bits/remote alarm sourced from TSER
E1TCR
E1 Transmit Control Register
1Eh
7
6
0
5
0
4
3
0
2
0
1
0
0
TFPT
0
TSiS
0
THDB3
0
HBE
PIN 55
0
0
0
0
0
0
0
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