参数资料
型号: DS26504LN+
厂商: Maxim Integrated Products
文件页数: 65/129页
文件大小: 0K
描述: IC T1/E1/J1 64KCC ELEMENT 64LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 160
功能: BITS 元件
接口: 64KCC,E1,T1
电路数: 1
电源电压: 3.14 V ~ 3.47 V
电流 - 电源: 150mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
包括: *
DS26504 T1/E1/J1/64KCC BITS Element
40 of 129
8. T1 FRAMER/FORMATTER CONTROL REGISTERS
The T1 framer portion of the DS26504 is configured via a set of five control registers. Typically, the
control registers are only accessed when the system is first powered up. Once the DS26504 has been
initialized, the control registers only need to be accessed when there is a change in the system
configuration. There are two receive control registers (T1RCR1 and T1RCR2), two transmit control
registers (T1TCR1 and T1TCR2), and a common control register (T1CCR). Each of these registers is
described in this section.
8.1 T1 Control Registers
Register Name:
T1RCR1
Register Description:
T1 Receive Control Register 1
Register Address:
03h
Bit #
7
6
5
4
3
2
1
0
Name
ARC
OOF1
OOF2
SYNCC
SYNCT
SYNCE
RESYNC
Default
0
HW
Mode
0
Bit 0: Resynchronize (RESYNC). When toggled from low to high, a resynchronization of the receive side framer is initiated.
Must be cleared and set again for a subsequent resync.
Bit 1: Sync Enable (SYNCE)
0 = auto resync enabled
1 = auto resync disabled
Bit 2: Sync Time (SYNCT)
0 = qualify 10 bits
1 = qualify 24 bits
Bit 3: Sync Criterion (SYNCC)
In D4 Framing Mode:
0 = search for Ft pattern, then search for Fs pattern
1 = cross-couple Ft and Fs pattern
In ESF Framing Mode:
0 = search for FPS pattern only
1 = search for FPS and verify with CRC6
Bits 4 and 5: Out-of-Frame Select Bits (OOF2, OOF1)
OOF2
OOF1
OUT-OF-FRAME
CRITERION
0
2/4 frame bits in error
0
1
2/5 frame bits in error
1
0
2/6 frame bits in error
1
2/6 frame bits in error
Bit 6: Auto Resync Criterion (ARC)
0 = resync on OOF or RLOS event
1 = resync on OOF only
Bit 7: Unused, must be set = 0 for proper operation.
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