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| 型号： | DS26504LN+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 7/129页 |
| 文件大小： | 0K |
| 描述： | IC T1/E1/J1 64KCC ELEMENT 64LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 160 |
| 功能： | BITS 元件 |
| 接口： | 64KCC，E1，T1 |
| 电路数： | 1 |
| 电源电压： | 3.14 V ~ 3.47 V |
| 电流 - 电源： | 150mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
| 包括： | * |
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DS26504 T1/E1/J1/64KCC BITS Element
104 of 129
TAP Controller State Machine
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of
JTCLK. See Figure 17-2.
Test-Logic-Reset
Upon power-up, the TAP controller is in the Test-Logic-Reset state. The instruction register contains the
IDCODE instruction. All system logic of the device operates normally.
Run-Test-Idle
The Run-Test-Idle is used between scan operations or during specific tests. The instruction register and
test registers remain idle.
Select-DR-Scan
All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the
controller into the Capture-DR state and initiates a scan sequence. JTMS HIGH during a rising edge on
JTCLK moves the controller to the Select-IR-Scan state.
Capture-DR
Data can be parallel-loaded into the test-data registers selected by the current instruction. If the
instruction does not call for a parallel load or the selected register does not allow parallel loads, the test
register remains at its current value. On the rising edge of JTCLK, the controller goes to the Shift-DR
state if JTMS is LOW, or it goes to the Exit1-DR state if JTMS is HIGH.
Shift-DR
The test-data register selected by the current instruction is connected between JTDI and JTDO and shifts
data one stage toward its serial output on each rising edge of JTCLK. If a test register selected by the
current instruction is not placed in the serial path, it maintains its previous state.
Exit1-DR
While in this state, a rising edge on JTCLK puts the controller in the Update-DR state, which terminates
the scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW puts the controller in
the Pause-DR state.
Pause-DR
Shifting of the test registers is halted while in this state. All test registers selected by the current
instruction retain their previous state. The controller remains in this state while JTMS is LOW. A rising
edge on JTCLK with JTMS HIGH puts the controller in the Exit2-DR state.
Exit2-DR
A rising edge on JTCLK with JTMS HIGH while in this state puts the controller in the Update-DR state
and terminates the scanning process. A rising edge on JTCLK with JTMS LOW enters the Shift-DR state.
Update-DR
A falling edge on JTCLK while in the Update-DR state latches the data from the shift register path of the
test registers into the data output latches. This prevents changes at the parallel output due to changes in
the shift register.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS26504LN+ | 功能描述:计时器和支持产品 E1/T1/J1/64Kcc Bits Element RoHS:否 制造商:Micrel 类型:Standard 封装 / 箱体:SOT-23 内部定时器数量:1 电源电压-最大:18 V 电源电压-最小:2.7 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Reel |
| DS26504LN+T&R | 制造商:Maxim Integrated Products 功能描述:T1/E1/J1 ENH BITS IC LQFP LF T&R - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC T1/E1/J1 64KCC ELEMENT 64LQFP |
| DS26504LN+T&R | 功能描述:网络控制器与处理器 IC E1/T1/J1/64Kcc Bits Element RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS26504LNB2 | 功能描述:网络控制器与处理器 IC E1/T1/J1/64Kcc Bits Element RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS26504LNB2+ | 功能描述:网络控制器与处理器 IC E1/T1/J1/64Kcc Bits Element RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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