参数资料
型号: DS2704G+T&R
厂商: Maxim Integrated Products
文件页数: 7/18页
文件大小: 0K
描述: IC EEPROM 1.25KBIT 6TDFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 10,000
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 1.25K(32B x 5 页)
接口: 1 线 串行
电源电压: 2.5 V ~ 5.5 V
工作温度: -30°C ~ 85°C
封装/外壳: 6-WDFN 裸露焊盘
供应商设备封装: 6-TDFN 裸露焊盘(3x3)
包装: 带卷 (TR)
DS2704: 1280-Bit EEPROM with SHA-1 Authentication
Table 3. 1-Wire Speed Control Function Commands
COMMAND
Set Overdrive
Clear Overdrive
Hex
8B
8D
FUNCTION
Sets 1-Wire interface timings to OVERDRIVE.
Sets 1-Wire interface timings to STANDARD.
(Factory Default)
EEPROM MEMORY
The DS2704 has a linear address space for access to the EEPROM data field. The Read Memory and Read
Data/Generate CRC Memory function commands provide DS2502 legacy read access to the lower 1024 bits of the
EEPROM data field. Read access to the entire EEPROM data field is provided by the Read All function command.
The Write Scratchpad, Read Scratchpad and Copy Scratchpad function commands provide write access to the
EEPROM data field. The EEPROM memory is organized as 5 pages of 32 bytes each as shown in Table 4.
EEPROM Data Field. All pages are read and write (R/W) accessible. When received from the factory, the entire
1280-bit EEPROM data field appears as logical 1’s.
Table 4. EEPROM Data Field
ADDRESS (HEX)
0000 – 001F
0020 – 003F
0040 – 005F
0060 – 007F
0080 – 009F
00A0 – FFFF
DESCRIPTION
PAGE 0 (32 bytes)
PAGE 1 (32 bytes)
PAGE 2 (32 bytes)
PAGE 3 (32 bytes)
PAGE 4 (32 bytes)
Reserved
READ/WRITE
R/W*
R/W*
R/W*
R/W*
R/W*
* Writing requires programming delay of t EEC
READ MEMORY [F0h]. The Read Memory command is used to read data from the lower 1024 bits (PAGE 0 to
PAGE 3) of the 1280-bit EEPROM data field. The bus master follows the command byte with a 2-byte address
(TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field. An 8-bit CRC of the
command byte and address bytes is computed by the DS2704 and read back by the bus master to confirm that the
correct command word and starting address were received. If the CRC is deemed to be incorrect by the bus
master, a reset pulse should be issued and the entire sequence repeated. If the CRC is deemed to be correct by
the bus master, read time slots can be issued to receive data from the EEPROM data field starting at the initial
address. The bus master can issue a reset pulse at any point or continue to issue read time slots until the end of
PAGE 3 of the data field is reached.
If reading continues through the end of PAGE 3, the bus master can issue eight additional read time slots and the
DS2704 will respond with a 8-bit CRC of all data bytes read from the initial starting byte through the last byte of
PAGE 3. Terminating the command transaction with a reset pulse prior to reaching the end of PAGE 3 results in a
loss of availability of the 8-bit CRC.
READ DATA/GENERATE 8-BIT CRC [C3h]
The Read Data/Generate 8-bit CRC command is used to read data from the lower 1024 bits (PAGE 0 to PAGE 3)
of the 1280-bit EEPROM data field. The bus master follows the command byte with a 2-byte address
(TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field. An 8-bit CRC of the
command byte and address bytes is computed by the DS2704 and read back by the bus master to confirm that the
correct command word and starting address were received. If the CRC is deemed to be incorrect by the bus
master, a reset pulse should be issued and the entire sequence repeated. If the CRC is deemed to be correct by
the bus master, read time slots can be issued to receive data from the EEPROM data field starting at the initial
address. The bus master can issue a reset pulse at any point or continue to issue read time slots until the end of
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