参数资料
型号: DS2776G+
厂商: Maxim Integrated Products
文件页数: 5/46页
文件大小: 0K
描述: IC FUEL GAUGE LI+ 2CELL 14-TDFN
产品培训模块: 1-Wire Communications
Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
功能: 燃料,电量检测计/监控器
电池化学: 锂离子(Li-Ion)、锂聚合物(Li-Pol)
电源电压: 4 V ~ 9.2 V
工作温度: -20°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 14-WFDFN 裸露焊盘
供应商设备封装: 14-TDFN-EP(3x5)
包装: 管件
产品目录页面: 1436 (CN2011-ZH PDF)
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with
Protector and Optional SHA-1 Authentication
ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE (DS2777/DS2778 ONLY)
(V DD = +4.0V to +9.2V, T A = -20°C to +70°C.)
PARAMETER
SCL Clock Frequency
SYMBOL
f SCL
(Note 4)
CONDITIONS
MIN
0
TYP
MAX
400
UNITS
kHz
Bus-Free Time Between a STOP
and START Condition
t BUF
1.3
μs
Hold Time (Repeated) START
Condition
Low Period of SCL Clock
High Period of SCL Clock
Setup Time for a Repeated
START Condition
t HD:STA
t LOW
t HIGH
t SU:STA
(Note 5)
0.6
1.3
0.6
0.6
μs
μs
μs
μs
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL
Signals
Fall Time of Both SDA and SCL
Signals
Setup Time for STOP Condition
Spike Pulse Widths Suppressed
by Input Filter
Capacitive Load for Each Bus
Line
SCL, SDA Input Capacitance
t HD:DAT
t SU:DAT
t R
t F
t SU:STO
t SP
C B
C BIN
(Notes 6, 7)
(Note 6)
(Note 8)
(Note 9)
0
100
20 +
0.1C B
20 +
0.1C B
0.6
0
0.9
300
300
50
400
60
μs
ns
ns
ns
μs
ns
pF
pF
Note 1: Accumulation bias and offset bias registers set to 00h. NBEN bit set to 0.
Note 2: Measurement made with V SRC = +8V, V GS driven with external +4.5V supply.
Note 3: Overvoltage (OV) and undervoltage (UV) delays (t OVD , t UVD ) are reduced to zero seconds if the OV or UV condition is
detected within 100ms of entering active mode.
Note 4: Timing must be fast enough to prevent the DS2777/DS2778 from entering sleep mode due to bus low for period > t SLEEP .
Note 5: f SCL must meet the minimum clock low time plus the rise/fall times.
Note 6: The maximum t HD:DAT need only be met if the device does not stretch the low period (t LOW ) of the SCL signal.
Note 7: This device internally provides a hold time of at least 75ns for the SDA signal (referred to the V IHMIN of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 8: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
Note 9: C B is total capacitance of one bus line in pF.
_______________________________________________________________________________________
5
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